Device with equaler circuit

Patent metadata

Field	Value
Publication number	US-10873484-B2
Application number	US-202016746722-A
Country	US
Kind code	B2
Filing date	Jan 17, 2020
Priority date	Jan 28, 2019
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

An integrated circuit is disclosed. The integrated circuit includes a first equalizer circuit and a second equalizer circuit. The first equalizer circuit is configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other. The second equalizer circuit coupled to the first equalizer circuit. The second equalizer circuit includes a first equalizer unit and a second equalizer unit. The first equalizer unit is configured to equalize the output signals, to generate odd data signals. The second equalizer unit is coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals. A method is also disclosed herein.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first equalizer circuit configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other; and
a second equalizer circuit coupled to the first equalizer circuit and comprising:
a first equalizer unit configured to equalize the output signals, to generate odd data signals; and
a second equalizer unit coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals.

2. The integrated circuit of claim 1 , further comprising:
a plurality of voltage shifting amplifier circuits configured to generate the offset voltages that are programmable, and configured to add the offset voltages to the input signal.

3. The integrated circuit of claim 1 , wherein the integrated circuit comprises:
a first differential amplifier;
a second differential amplifier including output terminals that are coupled to output terminals of the first differential amplifier, and including input terminals that are configured to receive a differential control signal; and
a digital-to-analog converter configured to convert a digital input signal into the differential control signal.

4. The integrated circuit of claim 1 , wherein the first equalizer unit comprises:
a plurality of summer circuits configured to add a first plurality of feedback signals to the output signals;
a plurality of slicer circuits coupled to the plurality of summer circuits, wherein a corresponding group of slicer circuits of the plurality of slicer circuits is configured to receive an output signal of a corresponding summer circuit of the plurality of summer circuits; and
a plurality of multiplexers coupled to the plurality of slicer circuits, wherein one of the plurality of multiplexers is configured to receive output signals of the corresponding group of slicer circuits and configured to output part of the odd data signals.

5. The integrated circuit of claim 4 , wherein the first equalizer unit further comprises:
a decoder configured to receive output signals of the plurality of multiplexers and configured to output binary data signals; and
a plurality of latches configured to receive the binary data signals and configured to output a first feedback signal of the first plurality of feedback signals.

6. The integrated circuit of claim 4 , wherein the first equalizer unit further comprises:
a first plurality of latches configured to receive the odd data signals and configured to generate a first feedback signal of the first plurality of feedback signals,
wherein the second equalizer unit is further configured to receive the first feedback signal to generate at least one of a second plurality of feedback signals.

7. The integrated circuit of claim 6 , wherein the first equalizer unit further comprises:
a second plurality of latches configured to receive the at least one of the second plurality of feedback signals, to generate at least one feedback signal, other than the first feedback signal, of the first plurality of feedback signals.

8. The integrated circuit of claim 1 , wherein the first equalizer circuit comprises a continuous time linear equalizer (CTLE) circuit, and the second equalizer circuit comprises a decision feedback equalizer (DFE) circuit.

9. An integrated circuit, comprising:
a continuous time linear equalizer (CTLE) circuit configured to receive and shift an input signal by a positive voltage, a zero voltage, and a negative voltage, and configured to generate output signals corresponding to the positive voltage, the zero voltage, and the negative voltage; and
a decision feedback equalizer (DFE) circuit comprising a first DFE unit and a second DFE unit that are coupled to the CTLE circuit,
wherein the first DFE unit is configured to equalize the output signals and configured to generate odd data signals, and configured to transmit the odd data signals to the second DFE unit for generating even data signals, and
the second DFE unit is configured to equalize the output signals and configured to generate the even data signals, and configured to transmit the even data signals to the first DFE unit for generating the odd data signals.

10. The integrated circuit of claim 9 , wherein the first DFE unit comprises:
a plurality of summer circuits configured to process the output signals, respectively, by adding a first plurality of feedback signals to each one of the output signals, wherein the first plurality of feedback signals are generated based on the odd data signals and at least one of a second plurality of feedback signals transmitted from the second DFE unit;
a plurality of groups of slicer circuits, wherein each group of slicer circuits of the plurality of groups of slicer circuits are configured to receive an output signal of a corresponding summer circuit of the plurality of summer circuits; and
a plurality of multiplexers, wherein each of the plurality of multiplexers is configured to receive output signals of a corresponding group of slicer circuits of the plurality of groups of slicer circuits and configured to output part of the odd data signals.

11. The integrated circuit of claim 10 , wherein the first DFE unit further comprises:
a decoder configured to receive output signals of the plurality of multiplexers and configured to output binary odd data signals, and configured to transmit the binary odd data signals to the second DFE unit,
wherein each of the plurality of multiplexers is configured to output, in response to binary even data signals transmitted from the second DFE unit, part of the odd data signals.

12. The integrated circuit of claim 11 , wherein the first DFE unit further comprises:
a first plurality of latches configured to receive the binary odd data signals and configured to generate a first feedback signal of the first plurality of feedback signals, and configured to transmit the first feedback signal to the second DFE unit for generating at least one of the second plurality of feedback signals.

13. The integrated circuit of claim 12 , wherein the first DFE unit further comprises:
a second plurality of latches configured to receive the at least one of the second plurality of feedback signals, to generate feedback signals, other than the first feedback signal, of the first plurality of feedback signals.

14. The integrated circuit of claim 10 , wherein at least one summer circuit of the plurality of summer circuits comprises:
a differential input circuit configured to receive a corresponding output signal of the output signals from the CTLE circuit, and configured to generate output signals to a corresponding group of slicer circuits of the plurality of groups of slicer circuits; and
a plurality of feedback circuits, wherein each one of the plurality of feedback circuits is configured to receive a corresponding feedback signal of the first plurality of feedback signals, and is configured to generate output signals, which correspond to the corresponding feedback signal, to be added to the output signals of the differential input circuit.

15. The integrated circuit of claim 14 , wherein the at least one summer circuit further comprises:
a level shifting circuit coupled to the differential input circuit and configured to shift voltage levels of the output signals of the differential input circuit; and
a common mode keeper circuit configured to keep a common mode voltage of the output signals of the differential input circuit constant.

16. The integrated

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Chih

Classifications

• H04L25/03885 Primary

  adaptive · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• H03F3/245

  with semiconductor devices only · CPC title