Powering clock tree circuitry using internal voltages

Patent metadata

Field	Value
Publication number	US-11132015-B2
Application number	US-201916271679-A
Country	US
Kind code	B2
Filing date	Feb 8, 2019
Priority date	Feb 8, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

First claim

What is claimed is:

1. An apparatus comprising:
a clock input buffer configured to receive first complementary clock signals and is coupled to a first supply voltage and a second supply voltage, wherein, responsive to the first complementary clock signals, the clock input buffer is configured to drive second complementary clock signals based on the first supply voltage and the second supply voltage; and
a divider circuit coupled to an internal voltage and the second supply voltage and configured to provide a divided clock signal based on the second complementary clock signals and the internal voltage and the second supply voltage, wherein the internal voltage is different than the first supply voltage.

2. The apparatus of claim 1 , Wherein the divider circuit further comprises an output buffer coupled to the first supply voltage and the second supply voltage and configured to receive the divided clock signal, wherein, in response to the divided clock signal, the output buffer is configured to drive a second divided clock signal based on the first supply voltage and the second supply voltage.

3. The apparatus of TT wherein the clock input buffer comprises:
a differential amplifier circuit configured to receive the first complementary clock signals and to provide intermediate complementary clock signals; and
a cross-coupled buffer configured to provide the second complementary clock signals based on the intermediate clock signals.

4. The apparatus of claim 1 , wherein the clock input buffer further comprises a pair of driver circuits coupled to the internal voltage and the second supply voltage and configured to receive the second complementary clock signals, wherein, in response to the second complementary clock signals, the pair of driver circuits are configured to provide third complementary clock signals to the divider circuit based on the internal voltage and the second supply voltage, wherein the divider circuit is configured to provide the divided clock signal in response to the third complementary clock signals.

5. The apparatus of claim 3 , wherein the differential amplifier circuit comprises:
a first differential amplifier configured to provide a first clock signal of the intermediate complementary clock signals based on receipt of a first clock signal of the first complementary clock signals at a first input and a second clock signal of the first complementary clock signals at a second input; and
a second differential amplifier configured to provide a second clock signal of the intermediate complementary clock signals based on receipt of the second clock signal of the first complementary clock signals at a first input and the first clock signal of the first complementary clock signals at a second input.

6. The apparatus of claim 5 , wherein the cross-coupled buffer comprises:
a first inverter coupled to the first supply voltage and the second supply voltage and configured to provide a first clock signal of the second complementary clock signals at a first output node based on receipt of the first clock signal of the intermediate complementary clock signals; and
a second inverter coupled to the first supply voltage and the second supply voltage and configured to provide a second clock signal of the second complementary clock signals at a second output node based on receipt of the second clock signal of the intermediate complementary clock signals.

7. The apparatus of claim 5 , wherein the cross-coupled buffer further comprises:
a first transistor coupled to the first supply voltage and configured to provide the first supply voltage to the second output node of the second inverter based on the value of the first output node of the first inverter; and
a second transistor coupled to the first supply voltage and configured to provide the first supply voltage to the first output node of the first inverter based on the value of the second output node of the second inverter.

8. The apparatus of claim 7 , wherein the first transistor and the second transistor are p-type transistors.

9. The apparatus of claim 1 , wherein, based on the second complementary clock signals and the internal voltage, the divider circuit is configured to provide a plurality of divided clock signals including the divided clock signal.

10. The apparatus of claim 9 , wherein the divider circuit is configured to shift a phase of the plurality of divided clock signals relative to one another.

11. The apparatus of claim 9 , wherein the divider circuit is configured to provide the plurality of divided clock signals having a frequency that is different than a frequency of the second complementary clock signals.

12. The apparatus of claim 11 , wherein the frequency of the plurality of divided clock signals is half of a frequency of the second complementary clock signals.

13. A method comprising:
receiving, at a clock input buffer, first complementary clock signals;
responsive to the first complementary clock signals, providing second complementary clock signals based on a first voltage and a second voltage; and
providing, via a divider circuit, a divided clock signal based on the second complementary clock signals and a third voltage and the second voltage, wherein a magnitude of the first voltage is different than a magnitude of the third voltage.

14. The method of claim 13 , further comprising driving, at the clock input buffer, third complementary clock signals responsive to the second complementary clock signals and based on the third voltage and the second voltage, wherein the divided clock signal is provided responsive to the third complementary dock signals.

15. The method of claim 13 , wherein the second complementary clock signals comprise a first clock signal and a second clock signal, the method further comprising cross-coupling first and second clock signals of the second complementary clock signals.

16. The method of claim 13 , further comprising driving a second divided clock signal responsive to the divided clock signal and based on the first voltage and the second voltage.

Assignees

• Micron Technology Inc

Inventors

• Asaki Kenji
• Tsukada Shuichi

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G11C7/225

  Clock input buffers · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title