Methods to embed magnetic material as first layer on coreless substrates and corresponding structures

Patent metadata

Field	Value
Publication number	US-11735537-B2
Application number	US-202217852003-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Mar 28, 2018
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

First claim

What is claimed is:

1. A method of forming an electronic package, comprising:
forming a first conductive layer over a dummy core;
forming a second conductive layer over the first conductive layer with a lithographic process;
forming a first barrier layer over exposed surfaces of the first conductive layer, the second conductive layer, and the dummy core;
forming a first layer over the first barrier layer, wherein the first layer comprises a magnetic material, and wherein a top surface of the first layer is substantially coplanar with a top surface of the second conductive layer; and
forming a second barrier layer over the first layer and the second conductive layer, wherein the first barrier layer and the second barrier layer entirely surround portions of the first layer.

2. The method of claim 1 , wherein the first layer and the first barrier layer are laminated together prior to being disposed over exposed surfaces of the first conductive layer, the second conductive layer, and the dummy core.

3. The method of claim 1 , wherein a portion of the first layer forms a portion of an inductor in the electronic package.

4. A method of fabricating an electronic package, the method comprising:
forming a first layer, wherein the first layer comprises a dielectric material;
forming a second layer over the first layer, wherein the second layer comprises a magnetic material having an uppermost surface;
forming a third layer over the second layer, wherein the third layer comprises a dielectric material, and wherein the third layer entirely covers a first surface of the second layer; and
forming a first conductive layer and a second conductive layer embedded within the second layer, wherein sidewalls of the first conductive layer and the second conductive layer are substantially vertical, and wherein the first conductive layer and the second conductive layer have an uppermost surface horizontally co-planar with the uppermost surface of the magnetic material of the second layer.

5. The method of claim 4 , wherein the first layer is a photoimageable dielectric (PID).

6. The method of claim 5 , wherein an opening through the first layer exposes a surface of the first conductive layer.

7. The method of claim 4 , wherein the second conductive layer comprises a vertical pillar.

8. The method of claim 4 , further comprising:
forming a magnetic block formed on a surface of the first layer opposite from the second layer.

9. The method of claim 8 , wherein the first conductive layer comprises a conductive trace between the magnetic block and the second layer.

10. The method of claim 9 , further comprising:
forming an inductor, wherein the inductor comprises portions of the first conductive layer, the second conductive layer, and the magnetic block, and wherein the inductor is a transmission line inductor, a spiral inductor, or a solenoid inductor.

11. The method of claim 4 , further comprising:
forming a fourth layer over the third layer, wherein the fourth layer is a dielectric material.

12. The method of claim 11 , further comprising:
forming a third conductive layer through the third layer;
forming a fourth conductive layer over the third layer;
forming a fifth conductive layer in the fourth layer; and
forming a sixth conductive layer over the fourth layer.

13. The method of claim 12 , further comprising:
forming a first solder resist layer over the fourth layer, wherein openings are formed into the solder resist layer to expose portions of the fifth conductive layer.

14. The method of claim 13 , further comprising:
forming a second solder resist layer over a surface of the first layer opposite the second layer.

15. The method of claim 14 , further comprising:
forming a conductive layer through the first layer, wherein the second solder resist comprises an opening to expose a portion of the conductive layer.

16. The method of claim 4 , wherein the electronic package is a coreless package.

17. A method of fabricating an electronic package, the method comprising:
forming a first layer, wherein the first layer comprises a magnetic material having an uppermost surface;
forming a first conductive layer and a second conductive layer embedded within the first layer, wherein the first conductive layer and the second conductive layer have an uppermost surface horizontally co-planar with the uppermost surface of the magnetic material of the first layer;
forming a first barrier layer along a bottom surface of the first layer and along sidewall surfaces of the first layer, wherein the first barrier layer separates the first layer from the first conductive layer and the second conductive layer; and
forming a second barrier layer over a top surface of the first layer.

18. The method of claim 17 , wherein the sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

19. The method of claim 17 , wherein a thickness of the first barrier layer is less than a thickness of the second barrier layer.

20. The method of claim 17 , further comprising:
forming a third conductive layer through the second barrier layer;
forming a fourth conductive layer over the second barrier layer;
forming a buildup layer over the second barrier layer, wherein the buildup layer comprises a dielectric material;
forming a fifth conductive layer through the buildup layer; and
forming a sixth conductive layer over the buildup layer.

21. The method of claim 20 , further comprising:
forming a first solder resist layer over the buildup layer; and
forming a second solder resist layer contacting a portion of the first barrier layer.

22. The method of claim 21 , further comprising:
forming a magnetic block formed on through an opening in the second solder resist layer; and
forming an inductor comprising portions of the first conductive layer, the first layer, and the magnetic block.

23. The method of claim 17 , wherein the electronic package is a coreless package.

Assignees

• Intel Corp

Inventors

• Xu Cheng
• Lee Kyu-Oh
• Zhao Junnan
• Jain Rahul
• Park Ji Yong
• Vadlamani Sai
• Kim Seo Young

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title