Unified translation miss queue for multiple address translation modes

Patent metadata

Field	Value
Publication number	US-11734188-B2
Application number	US-202117199315-A
Country	US
Kind code	B2
Filing date	Mar 11, 2021
Priority date	Mar 11, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

First claim

What is claimed is:

1. A unified memory address translation system comprising:
a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory;
a translation cache (XLTC) interface configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module;
at least one of a page table entry group (PTEG) search module or a segment table entry group (STEG) search module coupled to the translation queue module;
a unified translation walk address generation (UTWAG) module configured to provide a translation support for each mode of the different modes of translation request; and
a memory interface coupled between the UTWAG and the physical memory,
wherein each of the translation requests is processed by a sequence module of the translation queue module.

2. The system of claim 1 , wherein the XLTC interface, the PTEG search module STEG search module, and the translation queue module are shared by all translation modes.

3. The system of claim 1 , wherein the modes of translation requests comprise at least one of:
a hashed page table (HPT) request;
a segment table request;
a non-nested radix request; and
a nested radix request.

4. The system of claim 1 , wherein the sequence module of the translation queue module is configured to provide a round robin arbitration between the translation requests.

5. The system of claim 1 , wherein the translation supports of the UTWAG module include at least one of:
a partition table entry real address generation (PATE RA GEN);
a segment table entry group virtual address generation (STEG VA GEN) operative to provide a translation from an effective address (EA) to a virtual address (VA);
a segment table entry group real address generation (STEG RA GEN) operative to define an intermediate virtual address (STEG VA) to a real address (RA) translation;
a page table entry group real address generation (PTEG RA GEN);
a radix host real address generation (RADIX HOST RA GEN); or
a radix guest real address generation (RADIX GUEST RA GEN).

6. The system of claim 1 , further comprising a finite state machine coupled to each translation queue entry of the translation queue module.

7. The system of claim 6 , wherein the state machine is shared by all translation supports of the UTWAG module.

8. A method of providing a unified memory address translation, comprising:
receiving a plurality of translation requests for a real address (RA) of a physical memory, by a translation queue module;
allocating each of the plurality of translation requests to a translation walk queue entry of the translation queue module;
for each translation walk queue entry:
determining a starting virtual address (VA) and a translation mode from a corresponding translation request;
providing a VA and translation mode to a unified translation walk address generation (UTWAG) module comprising a plurality of translation supports that accommodate different translation modes; and
translating the VA to an RA, by the UTWAG module, based on the translation mode.

9. The method of claim 8 , wherein the plurality of translation requests is not of uniform mode.

10. The method of claim 8 , wherein the plurality of translation requests comprises at least one of:
a hashed page table (HPT) request;
a segment table request;
a non-nested radix request; or
a nested radix request.

11. The method of claim 8 , wherein a translation request of the plurality of translation requests is received by a translation cache (XLTC) interface from a translation cache (XLTC) operative to store one or more previous successful translation results.

12. The method of claim 11 , wherein the XLTC interface, one or more page table entry group (PTEG) search modules, and the translation queue module are shared by all translation modes.

13. The method of claim 11 , wherein the allocating of each translation request to one of the plurality of translation walk queue entries is upon determining that a matching previous result is not found in the XLTC.

14. The method of claim 8 , wherein each translation walk queue entry is different for each clock cycle of a processor.

15. The method of claim 8 , further comprising providing a round robin arbitration between the plurality of translation walk queue entries.

16. The method of claim 8 , wherein the translation supports of the UTWAG module provide at least one of:
a partition table entry real address generation (PATE RA GEN);
a segment table entry group virtual address generation (STEG VA GEN) providing an effective address (EA) to a virtual address (VA) translation;
a segment table entry group real address generation (STEG RA GEN) defining an intermediate virtual address (STEG VA) to a real address (RA) translation;
a page table entry group real address generation (PTEG RA GEN);
a radix host real address generation (RADIX HOST RA GEN); or
a radix guest real address generation (RADIX GUEST RA GEN).

17. The method of claim 8 , further comprising coupling a finite state machine to each translation queue entry of the translation queue module.

18. The method of claim 17 , wherein the state machine is shared by all translation modes.

19. A computing device comprising:
a processor;
a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory;
a translation cache (XLTC) interface configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module;
at least one of a page table entry group (PTEG) search module or a segment table entry group (STEG) search module coupled to the translation queue module;
a memory coupled to the processor;
a unified translation walk address generation (UTWAG) software module stored in the memory, wherein an execution of the UTWAG by the processor configures the computing device to provide a translation support for each mode of the different modes of translation request; and
a memory interface coupled between the UTWAG and the physical memory,
wherein a sequence module of the translation queue module is configured to process each of the translation requests.

20. The computing device of claim 19 , wherein the XLTC interface, the PTEG search modules, and the translation queue module are shared by all translation modes.

21. The computing device of claim 19 , wherein the modes of translation request comprise at least one of:
a hashed page table (HPT) request;
a segment table request;
a non-nested radix request; or
a nested radix request.

22. The computing device of claim 19 , wherein the translation supports of the UTWAG module include at least one of:
a partition table entry real address generation (PATE RA GEN);
a segment table entry group virtual address generation (STEG VA GEN) operative to provide an effective address (EA) to a virtual address (VA);
a segment table entry group real address generation (STEG RA GEN) operative to define an intermediate virtual address (STEG VA) to a real address (RA) translation;
a page table entry group real address generation (PTEG RA GEN);
a radix host real address generation (RADIX HOST RA GEN); or
a radix guest real address generation (RADIX GUEST RA GEN).

23. The computing device of claim 19 , furth

Assignees

• IBM

Inventors

• Wait Charles D
• Campbell David
• Truelove Jake
• Joyner Jody
• Kriegel Jon K
• Kincaid Glenn O

Classifications

• G06F12/1045 Primary

  associated with a data cache · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title