Handling address translation requests

Patent metadata

Field	Value
Publication number	US-2016259735-A1
Application number	US-201615019069-A
Country	US
Kind code	A1
Filing date	Feb 9, 2016
Priority date	Mar 2, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

First claim

I claim:

1 . A memory management unit comprising:
an interface configured to receive an address translation request from a device, the address translation request specifying a virtual address to be translated; and translation circuitry configured to translate the virtual address specified by the address translation request into an intermediate address different from a physical address directly specifying a memory location; wherein the interface is configured to provide an address translation response comprising the intermediate address to the device in response to the address translation request.

2 . The memory management unit according to claim 1 , wherein in response to a translated access request received by the interface from the device, the translated access request specifying the intermediate address, the translation circuitry is configured to translate the intermediate address into a corresponding physical address.

3 . The memory management unit according to claim 1 , wherein in response to a non-translated access request received by the interface from the device, the non-translated access request specifying a virtual address, the translation circuitry is configured to translate the virtual address into a corresponding physical address.

4 . The memory management unit according to claim 3 , wherein in response to the non-translated access request, the translation circuitry is configured to perform a first translation to translate the virtual address into a corresponding intermediate address, and to perform a second translation to translate the intermediate address into said corresponding physical address.

5 . The memory management unit according to claim 4 , wherein the translation circuitry is configured to perform the first translation based on first control data set under control of a first control program executed by a processing unit, and to perform the second translation based on second control data set under control of a second control program executed by the processing unit.

6 . The memory management unit according to claim 1 , comprising control circuitry configured to control processing of a memory access using the physical address obtained by the translation circuitry.

7 . The memory management unit according to claim 1 , wherein in a first address translation mode, in response to the address translation request the translation circuitry is configured to translate the virtual address into the intermediate address and the interface is configured to provide the address translation response specifying the intermediate address; and
in a second address translation mode, in response to the address translation request the translation circuitry is configured to translate the virtual address into the physical address and the interface is configured to provide the address translation response specifying the physical address.

8 . The memory management unit according to claim 7 , wherein the translation circuitry is configured to select whether to use the first address translation mode or the second address translation mode in dependence on control information accessible to the translation circuitry.

9 . The memory management unit according to claim 8 , wherein the control information specifies, separately for each of a plurality of devices or contexts, whether to use the first address translation mode or the second address translation mode for requests received from that device or context.

10 . The memory management unit according to claim 1 , wherein in the first address translation mode, in response to a translated access request received by the interface, the translation circuitry is configured to translate an intermediate address specified by the translated access request into a corresponding physical address to be used for a memory access; and
in the second address translation mode, in response to a translated access request received by the interface, the memory management unit is configured to provide the physical address specified by the translated access request to be used for a memory access.

11 . The memory management unit according to claim 10 , wherein the memory management unit has a plurality of operating modes including:
a performance mode in which, in response to a translated access request received by the interface, the memory management unit is configured to allow a memory access to proceed using an address specified by the translated access request without checking whether to use the first address translation mode or the second address translation mode; and a safety mode in which, in response to a translated access request received by the interface, the translation circuitry is configured to check whether to use the first address translation mode or the second address translation mode for the translated access request before allowing any memory access to proceed in response to the translated access request.

12 . The memory management unit according to claim 11 , wherein the memory management unit is configured to prohibit use of the first address translation mode when the memory management unit is in the performance mode.

13 . The memory management unit according to claim 1 , comprising a control storage element configured to store control information indicating whether the memory management unit is in the performance mode or the safety mode.

14 . A data processing apparatus comprising a memory management unit according to claim 1 .

15 . A memory management unit comprising:
means for receiving an address translation request from a device, the address translation request specifying a virtual address to be translated; means for translating the virtual address specified by the address translation request into an intermediate address different from a physical address directly specifying a memory location; and means for providing an address translation response comprising the intermediate address to the device in response to the address translation request.

16 . A method comprising:
receiving an address translation request from a device, the address translation request specifying a virtual address to be translated; translating the virtual address specified by the address translation request into an intermediate address different from a physical address directly specifying a memory location; and providing an address translation response to the device, the address translation response comprising the intermediate address.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Evans Matthew Lucien

Classifications

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/10 Primary

  Address translation · CPC title