Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator

Patent metadata

Field	Value
Publication number	US-10817291-B2
Application number	US-201916370915-A
Country	US
Kind code	B2
Filing date	Mar 30, 2019
Priority date	Mar 30, 2019
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of processing elements;
an interconnect network between the plurality of processing elements to transfer values between the plurality of processing elements; and
a first processing element of the plurality of processing elements comprising:
a plurality of input queues,
a configuration register within the first processing element to store a configuration value having:
a first portion that, when set to a first value that indicates a first mode, causes the first processing element to pass an input value to operation circuitry of the first processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the first processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the first processing element, and
a second portion that causes the first processing element to perform an operation indicated by the second portion of the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry,

an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value,
a plurality of output queues, and
an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

2. The apparatus of claim 1 , wherein, when at least one of the plurality of input queues stores the input value, the input controller is to send a not empty value to the operation circuitry of the first processing element to indicate the first processing element is to, when the first portion of the configuration value is set to the second value, perform the swizzle operation on the input value from the at least one of the plurality of input queues to form the swizzled input value, and then begin the operation on the swizzled input value.

3. The apparatus of claim 1 , wherein, when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element to indicate the first processing element is to, when the first portion of the configuration value is set to the second value, perform the swizzle operation on the input value stored in at least one of the plurality of input queues to form the swizzled input value, and then begin the operation on the swizzled input value.

4. The apparatus of claim 1 , wherein, when at least one of the plurality of input queues stores the input value, the input controller is to send a not empty value to the operation circuitry of the first processing element and when at least one of the plurality of output queues is not full, the output controller is to send a not full value to the operation circuitry of the first processing element, and the operation circuitry of the first processing element is to, when the first portion of the configuration value is set to the second value, swizzle the input value from the at least one of the plurality of input queues to form the swizzled input value, and then begin the operation on the swizzled input value.

5. The apparatus of claim 1 , wherein when the first portion of the configuration value is set to the second value, the swizzle operation replicates a lower portion of the input value into multiple locations in the swizzled input value.

6. The apparatus of claim 1 , wherein when the first portion of the configuration value is set to the second value, the swizzle operation replicates an upper portion of the input value into multiple locations in the swizzled input value.

7. The apparatus of claim 1 , wherein when the first portion of the configuration value is set to the second value, the swizzle operation swaps a lower portion and an upper portion of the input value in the swizzled input value.

8. The apparatus of claim 1 , wherein the first portion of the configuration value comprises:
at least a first bit corresponding to a first input queue of the plurality of input queues and that when set to a first value causes the first processing element to pass a first input value to the operation circuitry of the first processing element without modifying the first input value, and, when set to a second value, causes the first processing element to perform a first swizzle operation on the first input value to form a first swizzled input value before sending the first swizzled input value to the operation circuitry of the first processing element, and
at least a second, separate bit corresponding to a second input queue of the plurality of input queues and that when set to a first value causes the first processing element to pass a second input value to the operation circuitry of the first processing element without modifying the second input value, and, when set to a second value, causes the first processing element to perform a second, different swizzle operation on the second input value to form a second swizzled input value before sending the second swizzled input value to the operation circuitry of the first processing element.

9. A method comprising:
coupling a plurality of processing elements together by an interconnect network between the plurality of processing elements to transfer values between the plurality of processing elements;
storing a configuration value in a configuration register within a first processing element of the plurality of processing elements, the configuration value comprising:
a first portion that, when set to a first value that indicates a first mode, causes the first processing element to pass an input value to operation circuitry of the first processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the first processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the first processing element, and
a second portion that causes the first processing element to perform an operation indicated by the second portion of the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry;

controlling enqueue and dequeue of values into a plurality of input queues of the first processing element according to the configuration value with an input controller in the first processing element; and
controlling enqueue and dequeue of values into a plurality of output queues of the first processing element according to the configuration value with an output controller in the first processing element.

10. The method of claim 9 , wherein, when at least one of the plurality of input queues stores the input value, the input controller sends a not empty value to the operation circuitry of the first processing element to indicate the first processing element is to, when the first portion of the configuration value is set to the second value, perform the swizzle operation on the input value from the at least one of the plurality of input queues to form the swizzled input value, and then begin the operation on the swizzled input value.

11. The method of claim 9 , wherein, when at least one of the plurality of output queues is not full, the output controller sends a not full value to the operation circuitry of the first processing element to indicate the first processing element is to, when the first portion of the configuration value is set to the second value, perform the swizzle operation on the input value s

Assignees

• Intel Corp

Inventors

• Corbal Jesus
• Sharma Rohan
• Steely Jr Simon
• Ashok Chinmay
• Glossop Kent D
• Bradford Dennis
• Caprioli Paul
• Huot Louise
• Chofleming Kermin
• Tannenbaum Barry

Classifications

• G06F9/3005 Primary

  to perform operations for flow control · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/3897

  with adaptable data path · CPC title