Low overhead, high bandwidth re-configurable interconnect apparatus and method

Patent metadata

Field	Value
Publication number	US-11734174-B2
Application number	US-201916576687-A
Country	US
Kind code	B2
Filing date	Sep 19, 2019
Priority date	Sep 19, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

First claim

We claim:

1. An apparatus comprising:
a controller to generate a mode signal, wherein the mode signal indicates a mode of operation for a first set of two or more interconnects and a second set of two or more interconnects, wherein the mode of operation includes one of: a first mode, a second mode, or a third mode;
a first arbiter communicatively coupled to the controller, wherein the first arbiter is to configure the first set of two or more interconnects to be in one of the first, second, or third modes; and
a second arbiter communicatively coupled to the controller, wherein the second arbiter is to configure the second set of two or more interconnects to be in a same mode as the first set of two or more interconnects, p 1 wherein the first and second arbiters are operable to:
short inputs of the first set of two or more interconnects;
connect inputs of the first set of two or more interconnects to input ports or output ports of the first or second arbiter; or
disconnect an input of one of the first set of interconnects from input ports or output ports of the first or second arbiter.

2. The apparatus of claim 1 , wherein at least one of the first set of two or more interconnects and at least one of the second set of two or more interconnects is shielded by a power supply line or a ground line.

3. The apparatus of claim 1 , wherein the first mode is a bandwidth mode, wherein the first and second arbiters are to cause propagation of separate signals on the respective first and second sets of two or more interconnects.

4. The apparatus of claim 1 , wherein the second mode is a latency mode, wherein the first and second arbiters are to cause propagation of first same signals on the first set of two or more interconnects, and second same signals on the second set of two or more interconnects.

5. The apparatus of claim 1 , wherein the third mode is an energy mode, wherein the first and second arbiters are to cause propagation of signals on alternate interconnects of the first set of two or more interconnects and alternate interconnects of the second set of two or moreinterconnects.

6. The apparatus of claim 1 , wherein the controller is a power management unit, which also is operable to perform dynamic voltage and frequency scaling.

7. An apparatus comprising:
a power management unit (PMU) to generate a mode control; and
a mesh network of arbiters coupled to the PMU, wherein the mesh network of arbiters include:
a first arbiter communicatively coupled to the PMU and to receive the mode control;
a second arbiter communicatively coupled to the PMU and to receive the mode control;
a first pair of signal paths having a first driver and a second driver coupled to the first arbiter, and a first receiver and a second receiver coupled to the second arbiter; and
a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter, and a third receiver and a fourth receiver coupled to the first arbiter; wherein the first and second arbiters are to configure the first and second pairs of signal paths to be in one of a first, second, or third mode according to the mode control.

8. The apparatus of claim 7 , wherein the PMU is to perform dynamic voltage and frequency scaling.

9. The apparatus of claim 7 , wherein the first and second arbiters are to:
connect each input of the first pair of signal paths to each input port or output port of the first or second arbiter; or
short inputs of the first pair of signal paths to a same signal port of the first or second arbiter.

10. The apparatus of claim 7 , wherein the first and second arbiters are to:
open one electrical path of an input of one of the signal paths of the first pair of signal paths; or
connect each input of the first pair of signal paths to each input port or output port of the first or second arbiter.

11. The apparatus of claim 7 , wherein the first and second arbiters are to:
connect each input of the second pair of signal paths to each input port or output port of the first or second arbiter; or
short inputs of the second pair of signal paths to the same signal port of the first or second arbiter.

12. The apparatus of claim 7 , wherein the first and second arbiters are to:
open one electrical path of an input of one of the signal paths of the second pair of signal paths; or
connect each input of the first pair of signal paths to each input port or output port of the first or second arbiter.

13. The apparatus of claim 7 , wherein the first mode is a bandwidth mode, wherein the first and second arbiters are to cause propagation of separate signals on the first and second pairs of signal paths.

14. The apparatus of claim 7 , wherein the second mode is a latency mode, wherein the first and second arbiters are to cause propagation of first same signals on the first pair of signal paths, and second same signals on the second pair of signal paths.

15. The apparatus of claim 7 , wherein the third mode is an energy mode, wherein the first and second arbiters are to cause propagation of signals on alternate signal paths of the first and second pairs of signal paths.

16. A system comprising:
a memory;
a processor core coupled to the memory;
a power management unit (PMU) coupled to the processor core and to perform dynamic voltage and frequency scaling on the processor core;
a network-on-chip (NOC) comprising mesh or ring networks, wherein the NOC includes: a network of arbiters coupled to the PMU, wherein the network of arbiters include:
a first arbiter communicatively coupled to the PMU and to receive a mode control;
a second arbiter communicatively coupled to the PMU and to receive a mode control;
a first pair of signal paths having a first driver and a second driver coupled to the first arbiter, and a first receiver and a second receiver coupled to the second arbiter; and
a second pair of signal paths having a third driver and a fourth driver coupled to the second arbiter, and a third receiver and a fourth receiver coupled to the first arbiter, wherein the first and second arbiters are to configure the first and second pairs of signal paths to be in one of a first, second, or third mode according to the mode control; and

a wireless interface to allow the processor core to communicate with another device.

17. The system of claim 16 , wherein the first mode is a bandwidth mode, wherein the first and second arbiters are to cause propagation of separate signals on the first and second pairs of signal paths.

18. The system of claim 16 , wherein the second mode is a latency mode, wherein the first and second arbiters are to cause propagation of first same signals on the first pair of signal paths, and second same signals on the second pair of signal paths.

19. The system of claim 16 , wherein the third mode is an energy mode, wherein the first and second arbiters are to cause propagation of signals on alternate signal paths of the first and second pairs of signal paths.

Assignees

• Intel Corp

Inventors

• Liu Huichu
• Karnik Tanay
• Singh Tejpal
• Liu Yen-Cheng
• Subramanian Lavanya
• Kumashikar Mahesh
• Choday Sri Harsha
• Subramoney Sreenivas
• Vaidyanathan Kaushik
• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F11/2089

  Redundant storage control functionality · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F13/4204 Primary

  on a parallel bus · CPC title