Noc timing power estimating device and method thereof

Patent metadata

Field	Value
Publication number	US-2016149780-A1
Application number	US-201414585864-A
Country	US
Kind code	A1
Filing date	Dec 30, 2014
Priority date	Nov 24, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

First claim

What is claimed is:

1 . A network-on-chip (NoC) timing power estimating method, comprising:
estimating a plurality of transmission timings of a plurality of transmission units of at least a packet, the transmission timings indicating respective time points at which the transmission units enter/leave a plurality of traversed elements of the NoC; estimating respective circuit states and respective power states of the traversed elements of the NoC according to the transmission timings of the transmission units, wherein the circuit state indicates an operation state of the traversed element, and the power state is related to the circuit state; and estimating power consumption of the NoC according to the power states of the traversed elements of the NoC.

2 . The timing power estimating method according to claim 1 , wherein, the step of estimating the transmission timings of the transmission units comprises:
determining a routing path of the packet according to at least a packet parameter and a routing parameter of the NoC; performing arbitration to determine which packet gains a channel usage right if a plurality of routing paths of a plurality of packets conflict; calculating the transmission timings of the transmission units; and updating the circuit states of the traversed elements, and calculating a release timing of the channel usage right, to obtain a usage timing at which another packet gains the channel usage right.

3 . The timing power estimating method according to claim 2 , wherein,
according to whether the routing parameter is a dynamic routing or a static routing, determining whether update of the circuit states of the traversed elements affects the routing path of the packet.

4 . The timing power estimating method according to claim 2 , wherein, the step of calculating the transmission timings of the transmission units comprises:
determining the release timing (t stage[i]release ) at which an i-th router stage[i]is is released by the packet, wherein “i” is a positive integer; determining a buffer passing time (Δt passBUFFER ) required for one of the transmission units of the packet to pass through a buffer if no congestion; determining, when the buffer is full, a buffer allowed write time (Δt syncBUFFER ) between when one of the transmission units of the packet is read from the buffer and when a next transmission unit of the transmission units of the packet is written to the buffer; and determining whether a congestion occurs.

5 . The timing power estimating method according to claim 4 , wherein, the step of determining whether the congestion occurs comprises:
determining a sum of a first header entering time (t stage[i−1]flit[0] ) at which a header transmission unit flit[0] of the packet enters an (i−1)-th router stage[i−1] plus the buffer passing time (Δt passBUFFER ) required for the header transmission unit flit[0] to pass through the buffer; and comparing the sum with the release timing (t stage[i]release ) at which the i-th router stage[i] is released, to determine whether the congestion occurs.

6 . The timing power estimating method according to claim 5 , wherein, in a single-cycle router architecture,
if the congestion occurs, it is determined that a second header entering time (t stage[i]flit[0] ) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t stage[i]release ) at which the i-th router stage[i] is released plus a clock cycle; if the congestion does not occur, it is determined that the second header entering time (t stage[i]flit[0] ) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to the first header entering time (t stage[i−1]flit[0] ) at which the header transmission unit flit[0] enters the (i−1)-th router stage[i−1] plus the buffer passing time (Δt passFIFO ) required for the header transmission unit flit[0] to pass through the buffer.

7 . The timing power estimating method according to claim 6 , wherein, in the single-cycle router architecture,
a j-th transmission unit entering time (t stage[i]flit[j] ) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “j” is a positive integer:
the j-th transmission unit entering time (t stage[i]flit[j] ) is equivalent to a sum of a (j−1)-th transmission unit entering time (t stage[i]flit[j-1] ) at which a (j−1)-th transmission unit (flit[j−1]) of the packet enters the i-th router stage[i] plus k clock cycles clk stage[i] of the i-th router stage[i], wherein “k” is a positive integer;
the j-th transmission unit entering time (t stage[i]flit[j] ) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t stage[i−1]flit[j] ) at which the j-th transmission unit flit[j] enters the (i−1)-th router stage[i−1] plus the buffer passing time (Δt passFIFO ) required for the j-th transmission unit flit[j] to pass through the buffer; and
if the buffer having a depth of “d” is full, it is determined that the j-th transmission unit time (t stage[i]flit[j] ) at which the j-th transmission unit flit[j] enters the i-th router stage[i] is greater than a sum of a time (t stage[i+1]flit[j-d-1] ) at which a (j-d−1)-th transmission unit flit[j-d−1] enters an (i+1)-th router stage[i+1] plus the buffer allowed write time (Δt synFIFO ) at which the (j−1)-th transmission unit flit[j−1] is allowed to be written to the buffer, wherein “d” is a positive integer.

8 . The timing power estimating method according to claim 5 , wherein, in a 2-stage router architecture,
if the congestion occurs, it is determined that a second header entering time (t stage[i]flit[0] ) at which the header transmission unit flit[0] enters the i-th router stage[i] is equivalent to a sum of the release timing (t stage[i]release ) at which the i-th router stage[i] is released plus a clock cycle; and if the congestion does not occur, it is determined that the second header entering time (t stage[i]flit[0] ) at which the header transmission unit flit[0] enters the i-th router stage[i]is equivalent to a sum of the first header entering time (t stage[i−1]flit[0] ) at which the header transmission unit flit[0] enters the (i−1)-th router stage[i−1] plus the buffer passing time (Δt passFIFO ) required for the header transmission unit flit[0] to pass through the buffer and further plus the clock cycle.

9 . The timing power estimating method according to claim 8 , wherein, in the 2-stage router architecture,
a j-th transmission unit entering time (t stage[i]flit[j] ) at which a j-th transmission unit flit[j] of the packet enters the i-th router stage[i] satisfies following conditions, wherein “j” is a positive integer:
the j-th transmission unit entering time (t stage[i]flit[j] ) is equivalent to a (j−1)-th transmission unit entering time (t stage[i]flit[j-1] ) at which a (j−1)-th transmission unit (flit[j−1]) of the packet enters the i-th router stage[i] plus k clock cycles clk stage[i] of the i-th router stage[i], wherein “k” is a positive integer;
the j-th transmission unit entering time (t stage[i]flit[j] ) at which the j-th transmission unit flit[j] of the packet enters the i-th router stage[i] is greater than a sum of a time (t stage[i−1]flit[j] ) at which the j-th transmission unit flit[j] enters the (i−1)-th router stage[i−1] plus the buffer passing time (Δt passFIFO ) required for the j-th transmission unit flit[j] to pass through the buffer; and
if the buffer having a depth of “d” is full, it is determined that the j-th transmission unit time (t stage[i]flit[j] ) at which the j-th transmission unit flit[j] enters the i-th router s

Assignees

• Ind Tech Res Inst

Inventors

• Hsu Ting-Shuo
• Liou Jing-Jia
• Shen Jih-Sheng
• Lu Juin-Ming

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F15/7825 Primary

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F1/32

  Means for saving power · CPC title