Storage device and system of controlling operation through flow control monitoring

Patent metadata

Field	Value
Publication number	US-11733872-B2
Application number	US-202217706137-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Sep 28, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A system includes a transmission device and a reception device that are connected through a link. The reception device includes a reception buffer configured to receive and store transaction layer packets and a reception flow controller configured to generate flow control packets by monitoring an occupation state of the reception buffer. The transmission device includes a transmission buffer, a transmission flow controller and a dynamic frequency controller. The transmission buffer stores pending transaction layer packets to be transferred to the reception device. The transmission flow controller controls a flow of transaction layer packets to be transferred to the reception device based on the flow control packets received from the reception device. The dynamic frequency controller controls a frequency of an internal clock signal of the transmission device by monitoring a state of the transmission buffer and a state of the transmission flow controller.

First claim

What is claimed is:

1. A system comprising:
a transmission device and a reception device that are connected through a link,
the reception device including:
a reception buffer configured to receive and store transaction layer packets; and
a reception flow controller configured to generate flow control packets by monitoring an occupation state of the reception buffer,

the transmission device including:
a transmission buffer configured to store pending transaction layer packets to be transferred to the reception device;
a transmission flow controller configured to control a flow of transaction layer packets to be transferred to the reception device based on the flow control packets received from the reception device; and
a dynamic frequency controller configured to control a frequency of an internal clock signal of the transmission device by monitoring a state of the transmission buffer and a state of the transmission flow controller.

2. The system of claim 1 , wherein the transmission flow controller is configured to:
determine whether a storage space of the reception buffer is insufficient to store the transaction layer packets, based on a difference between a limit credit and a consumed credit where the limit credit is updated based on an allocated credit included in the flow control packets and the consumed credit corresponds to a number of the transaction layer packets that are transferred to the reception device; and
block transmission of the transaction layer packets to the reception device when the transmission flow controller determines that the storage space of the reception buffer is insufficient to store the transaction layer packets.

3. The system of claim 1 , wherein the dynamic frequency controller is configured to increase the frequency of the internal clock signal when a flow delay state occurs such that a number of the pending transaction layer packets stored in the transmission buffer is equal to or greater than one and the transmission flow controller blocks the transmission of the transaction layer packets to the reception device.

4. The system of claim 3 , wherein the dynamic frequency controller is configured to set a plurality of step frequencies and increase the frequency of the internal clock signal step by step starting from a minimum frequency among the plurality of step frequencies until the frequency of the internal clock signal reaches a maximum frequency among the plurality of step frequencies.

5. The system of claim 4 , wherein the dynamic frequency controller is configured to initialize the frequency of the internal clock signal to the minimum frequency when resetting of the link is completed.

6. The system of claim 4 , wherein the dynamic frequency controller is configured to determine periodically whether the flow delay state occurs and increase the frequency of the internal clock signal by one step whenever it is determined that the flow delay state occurs, until the frequency of the internal clock signal reaches the maximum frequency.

7. The system of claim 4 , wherein the dynamic frequency controller is configured to maintain the frequency of the internal clock signal at the maximum after the frequency of the internal clock signal reaches the maximum frequency and until the link is reset.

8. The system of claim 4 , wherein the dynamic frequency controller is configured to decrease the frequency of the internal clock signal when the number of the pending transaction layer packets stored in the transmission buffer is smaller than a reference number and a smooth flow state occurs such that the transmission flow controller allows the transmission of the transaction layer packets to the reception device.

9. The system of claim 8 , wherein the dynamic frequency controller is configured to determine periodically whether the smooth flow state occurs and decrease the frequency of the internal clock signal by one step whenever it is determined that the smooth flow state occurs, until the frequency of the internal clock signal reaches the minimum frequency.

10. The system of claim 1 , wherein dynamic frequency controller is configured to increase the frequency of the internal clock signal when a difference between a limit credit and a consumed credit is smaller than a first reference credit where the limit credit is updated based on an allocated credit included in the flow control packets and the consumed credit corresponds to a number of the transaction layer packets that are transferred to the reception device.

11. The system of claim 10 , wherein the dynamic frequency controller is configured to decrease the frequency of the internal clock signal when the difference between the limit credit and the consumed credit is greater than a second reference credit where the second reference credit is greater than the first reference credit.

12. The system of claim 1 , wherein the dynamic frequency controller is configured to determine, by a first cyclic period, whether to increase the frequency of the internal clock signal and determine, by a second cyclic period, whether to decrease the frequency of the internal clock signal, where the second cyclic period is longer than the first cyclic period.

13. The system of claim 1 , wherein the internal clock signal corresponds to a PIPE (PHY Interface for PCI Express) clock signal that is used to synchronize signal transfer between a PHY layer and an internal logic circuit of the transmission device.

14. The system of claim 1 , wherein the dynamic frequency controller is configured to increase the frequency of the internal clock signal to increase a speed of a flow control update operation by the transmission device when a transfer delay from the transmission device to the reception device occurs, regardless of a frequency of a bit rate clock signal that is used to control transfer speed between the transmission device and the reception device.

15. The system of claim 1 , further comprising:
a retimer disposed between the transmission device and the reception device.

16. The system of claim 1 , wherein the transmission device and the reception device are connected through a peripheral component interconnect express (PCIe) link according to PCIe standards.

17. A storage device commented to a host device through a peripheral component interconnect express (PCIe) link according to PCIe standards, comprising:
a nonvolatile memory device configured to store data; and
a storage controller configured to control the nonvolatile memory device,
the storage controller including:
a transmission buffer configured to store pending transaction layer packets to be transferred to the host device;
a transmission flow controller configured to control a flow of transaction layer packets to be transferred to the host device based on flow control packets received from the host device; and
a dynamic frequency controller configured to control a frequency of an internal clock signal of the storage controller by monitoring a state of the transmission buffer and a state of the transmission flow controller.

18. The storage device of claim 17 , wherein the dynamic frequency controller is configured to increase the frequency of the internal clock signal when a flow delay state occurs such that a number of the pending transaction layer packets stored in the transmission buffer is equal to or greater than one and the transmission flow controller blocks the transmission of the transaction layer packets to the host device.

19. The storage device of claim 18 , wherein the dynamic frequency controll

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jaehwan
• Jun Walter
• Kim Jaeeun
• Kim Jihoon
• Myung Kihyeon
• Yoo Hyunjung
• Lee Jungwoo

Classifications

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F2213/0026

  PCI express · CPC title