Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-11093166-B2
Application number	US-201916241488-A
Country	US
Kind code	B2
Filing date	Jan 7, 2019
Priority date	Apr 17, 2014
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

First claim

What is claimed is:

1. A method of operating a non-volatile memory system, the non-volatile memory system including a memory controller, a plurality of three-dimensional NAND flash memory chips and at least two ports, the method comprising:
receiving table information including temperature-dependent performance level information upon an initial operation of the non-volatile memory system, in response to an in-band command received through a host interface communicating with a host based on a non-volatile memory express (NVMe) protocol;
storing the table information in a volatile memory of the memory controller;
detecting an internal temperature of the non-volatile memory system by a temperature sensor of the memory controller;
automatically throttling a performance level of the non-volatile memory system by the memory controller according to a result of detecting the internal temperature of the non-volatile memory system without intervention from the host; and
providing current internal temperature information and performance level information to the host in response to a request from the host,
wherein the temperature-dependent performance level information includes a plurality of entries including at least a first entry and a second entry, and each of the first and second entries comprises temperature range information and performance level information,
wherein, when the detected internal temperature is specified within a temperature range of the first entry, a performance throttling level of the non-volatile memory system is set to a performance level of the first entry,
wherein, when the detected internal temperature is specified within a temperature range of the second entry, the performance throttling level of the non-volatile memory system is set to the performance level of the second entry, and
wherein the performance level corresponding to the first entry and the second entry are lower than a normal performance level.

2. The method of claim 1 , wherein the table information is received from the host during a boot-up operation of the memory system or a run-time operation of the memory system.

3. The method of claim 1 , further comprising:
receiving a command requesting setting of the table information,
wherein the memory system stores the table information in response to the received command.

4. The method of claim 1 , wherein the table information is updated in the volatile memory when a boot-up operation of the memory system is performed.

5. The method of claim 1 , wherein a frequency of an internal clock of the memory system is changed based on the performance level information of the table information.

6. The method of claim 1 , wherein a delay of a first confirm command corresponding to a first command received from the host is changed based on the performance level information of the table information.

7. The method of claim 1 , wherein
a number of three-dimensional NAND flash memory chips to be simultaneously accessed from among the plurality of three-dimensional NAND flash memory chips is changed based on the performance level information of the table information.

8. The method of claim 1 ,
wherein, when the detected internal temperature is changed from a temperature range of the first entry to a temperature range of the second entry as the internal temperature of the memory system increases, an operation performance of the memory system is decreased to a performance level of the second entry for decreasing the internal temperature.

9. The method of claim 8 , wherein, when the detected internal temperature is changed from the temperature range of the second entry to the temperature range of the first entry as the internal temperature of the memory system decreases, the operation performance of the memory system is increased to a performance level of the first entry for increasing the operation performance.

10. The method of claim 8 , wherein the plurality of entries further includes a third entry,
wherein, when the detected internal temperature is changed from the temperature range of the second entry to a temperature range of the third entry as the internal temperature of the memory system increases, the operation performance of the memory system is further decreased from the performance level of the second entry to a performance level of the third entry.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Seok
• Kim Dae-Ho
• Oh Yong-Geun
• Moon Sung-Jin

Classifications

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0653 Primary

  Monitoring storage devices or systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title