Resistive random-access memory device with step height difference

Patent metadata

Field	Value
Publication number	US-11730070-B2
Application number	US-201916286912-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Feb 27, 2019
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

First claim

What is claimed is:

1. A method, comprising:
forming a first electrode within a trench of a dielectric layer, wherein the first electrode has a maximum width that is less than a width of the trench and does not extend beyond the width of the trench;
recessing an area of the first electrode;
depositing a first portion of a metal oxide layer within the area of the first electrode and directly adjacent a sidewall of a barrier metal layer within the trench, and depositing a second portion of the metal oxide layer over and directly adjacent the barrier metal layer; and
forming a second electrode directly adjacent and over the metal oxide layer, wherein a maximum width of the second electrode is greater than the width of the trench.

2. The method of claim 1 , wherein one or more corner regions are present in the metal oxide layer between the first electrode and the second electrode based on the recessing the area of the first electrode prior to the depositing the metal oxide layer.

3. The method of claim 1 , further comprising:
enhancing a localized electrical field as a function of one or more corner regions being present in the metal oxide layer between the first electrode and the second electrode.

4. The method of claim 1 , wherein the forming the first electrode comprises forming one or more corners comprising an under-convex-shape.

5. The method of claim 1 , wherein the forming the first electrode comprises forming a three-dimensional shaped first electrode in the trench of the dielectric layer.

6. The method of claim 1 , wherein the forming the first electrode comprises forming one or more corners using chemical mechanical processing and wet etch processes.

7. The method of claim 1 , wherein the trench is a three-sided trench and wherein the barrier metal layer is a three sided barrier metal layer.

Assignees

• IBM

Inventors

• Miyazoe Hiroyuki
• Kim Seyoung
• Ray Asit
• Ando Takashi

Classifications

• H10N70/841 Primary

  Electrodes · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title