Resistive random access memory (RRAM) with improved forming voltage characteristics and method for making

Patent metadata

Field	Value
Publication number	US-9985203-B2
Application number	US-201314081916-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Nov 15, 2013
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.

First claim

What is claimed is:

1. A resistive random access memory (RRAM), comprising:
a bottom electrode over a substrate, the bottom electrode having a first upper surface and a second uppermost surface with one step transitioning from the first upper surface to the second uppermost surface, the one step being a first step, the first upper surface lower than the second uppermost surface, a resistance of the bottom electrode being independent of a voltage applied to the RRAM that is within an operational voltage range of the RRAM, the first upper surface being a planar surface that extends from an exterior sidewall of the bottom electrode to the first step, the bottom electrode having a sidewall connecting the first upper surface and the second uppermost surface, the sidewall forming an acute angle with the first upper surface;
a resistive material layer over and on the first step transitioning from the first upper surface to the second uppermost surface of the bottom electrode, the resistive material layer having a second step corresponding to the first step; and
a top electrode contacting the resistive material layer and covering the second step, the bottom electrode being between the top electrode and the substrate, the top electrode having a third step corresponding to the second step, a resistance of the top electrode being independent of the voltage applied to the RRAM that is within the operational voltage range of the RRAM, the resistive material layer having a same material composition extending from the bottom electrode to the top electrode, the bottom electrode, the resistive material layer, and top electrode having coterminous sidewalls.

2. The RRAM of claim 1 , wherein a height of the first step transitioning from the first upper surface to the second uppermost surface is less than 50 angstroms.

3. The RRAM of claim 1 , wherein a ratio of a height of the first step transitioning from the first upper surface to the second uppermost surface to a height of the first upper surface of the bottom electrode is less than 30%.

4. The RRAM of claim 1 , wherein the top electrode comprises a tantalum nitride layer over a titanium layer.

5. The RRAM of claim 1 , wherein the top electrode has a thickness less than 3000 angstroms.

6. The RRAM of claim 1 , further comprising a bottom electrode contact overlapping a face of the first step transitioning from the first upper surface to the second uppermost surface in a top view.

7. The RRAM of claim 4 , further comprising a capping layer interposed between the top electrode and the resistive material layer, the capping layer comprising hafnium, platinum, or tantalum.

8. The RRAM of claim 1 , wherein the top electrode comprises:
a first conductive layer contacting the resistive material layer; and
a second conductive layer over the first conductive layer, wherein the second conductive layer is formed of a different material than the first conductive layer, wherein an upper surface of the second conductive layer distal the first conductive layer is planar.

9. The RRAM of claim 8 , wherein a lower surface of the second conductive layer facing the first conductive layer is planar and is parallel to the upper surface of the second conductive layer.

10. A resistive random access memory (RRAM) array, comprising:
a plurality of RRAM pairs over a substrate and organized in columns and rows, each RRAM pair having:
two RRAM structures, each having:
a bottom electrode having a first edge with a first upper surface, a second edge with a second upper surface, a sidewall between the first edge and the second edge and between the first upper surface and the second upper surface, and a single protruded step portion transitioning from the first upper surface to the second upper surface, the second upper surface being at a higher level than the first upper surface, the first upper surface being planar and extending from an outermost sidewall of the bottom electrode to the single protruded step portion, the sidewall intersecting the first upper surface at an angle smaller than 90 degrees, a resistance of the bottom electrode being independent of a voltage applied to the RRAM array, the voltage being within an operational voltage range of the RRAM array;
a resistive material layer covering the single protruded step portion of the bottom electrode, the resistive material layer having a first step corresponding to the single protruded step portion of the bottom electrode, the bottom electrode disposed between the resistive material layer and the substrate; and
a top electrode over the resistive material layer and covering the first step of the resistive material layer, the top electrode having a second step corresponding to the first step of the resistive material layer, a resistance of the top electrode being independent of the voltage applied to the RRAM array, the resistive material layer having a same material composition and extending continuously from the bottom electrode to the top electrode;

wherein:
the bottom electrode, the resistive material layer, and top electrode have opposing coterminous sidewalls; and
the single protruded step portions in each RRAM pair are mirror images.

11. The RRAM array of claim 10 , further comprising a transistor connected to the bottom electrode or the top electrode of each RRAM structure.

12. The RRAM array of claim 10 , wherein the resistive material layer has a thickness less than about 300 angstroms.

13. The RRAM array of claim 10 , wherein the resistive material layer comprises a high-k dielectric.

14. The RRAM array of claim 10 , wherein the RRAM pairs in adjacent rows are mirror images of each other.

15. The RRAM of claim 10 , wherein the top electrode has a first conductive layer and a second conductive layer, the first conductive layer being between the second conductive layer and the resistive material layer, wherein the first conductive layer and the second conductive layer are formed of different materials.

16. The RRAM of claim 15 , wherein the first conductive layer is formed of a metal, and the second conductive layer is formed of doped polysilicon.

17. A resistive random access memory (RRAM), comprising:
a first RRAM structure over a substrate and a second RRAM structure over the substrate, the first RRAM structure having a bottom electrode layer, a resistive material layer, and a top electrode layer, wherein the bottom electrode layer, the resistive material layer, and the top electrode layer have coterminous sidewalls, wherein the top electrode layer extends further from the substrate than the bottom electrode layer;
the bottom electrode layer having a first edge substantially perpendicular to a first upper surface, a second edge substantially perpendicular to a second upper surface, a first sidewall between the first edge and the second edge and connecting the first upper surface and the second upper surface, a third edge substantially perpendicular to a third upper surface, and a fourth edge substantially perpendicular to a fourth upper surface, a second sidewall between the third edge and the fourth edge and connecting the third upper surface and the fourth upper surface, a resistance of the bottom electrode layer being independent of a normal operational voltage applied to the RRAM, wherein:
the first RRAM structure comprises the first edge, the first sidewall, and the second edge;
the second RRAM structure comprises the third edge, the second sidewall, and the fourth edge;
the first upper surface is above the second upper surface, the first sidewall intersecting the second upper surface at an a

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jonathan Tehan
• Chou Chung-Cheng
• Lee Po-Hao
• Tu Kuo-Chi

Classifications

• H01L27/2463

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/1273

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic