Semiconductor memory

Patent metadata

Field	Value
Publication number	US-11729973-B2
Application number	US-202117160563-A
Country	US
Kind code	B2
Filing date	Jan 28, 2021
Priority date	Sep 19, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

First claim

The invention claimed is:

1. A semiconductor memory comprising:
a substrate;
a control circuit on the substrate;
a first memory cell array disposed above the control circuit, the first memory cell array including a plurality of first conductors stacked in a first direction crossing the substrate, and a first pillar extending through the first conductors and forming intersections with the first conductors, at least one of the intersections being configured to function as a memory cell;
an insulation film disposed above the first memory cell array;
a first external connection electrode configured for connecting with an external memory controller and disposed above the first memory cell array; and
a plurality of first vias respectively extending through the insulation film, respectively overlapping with the first external connection electrode in the first direction, and respectively electrically connecting the first external connection electrode to the control circuit, wherein
the plurality of first vias are arranged in at least one line in a second direction along one side of the substrate crossing the first direction.

2. The memory of claim 1 , wherein
the first external connection electrode and the first conductors are insulated from each other.

3. The memory of claim 1 , wherein
the control circuit comprises a sense amplifier connected to the first pillar.

4. The memory of claim 1 , wherein
the control circuit comprises a row decoder connected to the first conductors.

5. The memory of claim 1 , wherein
the control circuit comprises an input/output circuit configured to control communication between the first memory cell array and the external memory controller via the first external connection electrode.

6. The memory of claim 1 , further comprising:
a portion to join together opposing metals disposed between the first memory cell array and the control circuit, respectively.

7. The memory of claim 6 , wherein
the metals are copper.

8. The memory of claim 1 , wherein
the first pillar is absent between the first external connection electrode and the substrate.

9. The memory of claim 8 , wherein
ends of the first conductors are provided in a staircase manner and located between the first external connection electrode and the substrate.

10. The memory of claim 9 , wherein
the ends are free from connections of conductors for connecting the first memory cell array with the control circuit.

11. The memory of claim 1 , further comprising:
a second memory cell array disposed between the control circuit and the first memory cell array, the second memory cell array including a plurality of second conductors stacked in the first direction, and a second pillar extending through the second conductors and forming intersections with the second conductors, each of the intersections being configured to function as a memory cell;
a second external connection electrode disposed above the second memory cell array; and
a plurality of second vias respectively extending through the insulation film, respectively overlapping with the second external connection electrode in the first direction, and respectively electrically connecting the second external connection electrode to the control circuit.

12. The memory of claim 11 , wherein
the plurality of first vias and the plurality of second vias are arranged in line in a second direction crossing the first direction.

13. The memory of claim 12 , wherein
the second direction is along one side of the substrate.

Assignees

• Kioxia Corp

Inventors

• Tagami Masayoshi
• Iijima Jun
• Katsumata Ryota
• Higashi Kazuyuki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/333

  Compression bonding · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/301

  Bonding techniques, e.g. hybrid bonding · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title