Configurable wideband split LNA

US11728837B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11728837-B2
Application numberUS-202117366614-A
CountryUS
Kind codeB2
Filing dateJul 2, 2021
Priority dateJan 8, 2019
Publication dateAug 15, 2023
Grant dateAug 15, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.

First claim

Opening claim text (preview).

The invention claimed is: 1. A radio frequency (RF) receiver front-end comprising: a low noise amplifier (LNA) block; a selectively bypassable source follower amplifier stage, and a configurable output matching network, wherein the LNA block is selectively connectable to either of the selectively bypassable source follower amplifier stage or the configurable output matching network based on a selected bandwidth and/or a selected gain. 2. The RF receiver front-end of claim 1 , wherein a bandwidth and a gain of the RF receiver front-end is adjustable based on a bypass state of the selectively bypassable source follower amplifier stage and a configuration state of the configurable output matching network. 3. The RF receiver front-end of claim 2 , wherein: in a first state: the LNA block is connected to the configurable output matching network; the LNA block is disconnected from the selectively bypassable source follower amplifier stage; and the selectively bypassable source follower amplifier stage is bypassed by having a gate terminal of the selectively bypassable source follower amplifier stage shorted to ground; in a second state: the LNA block is disconnected from the configurable output matching network; and the LNA block is connected to the selectively bypassable source follower amplifier stage. 4. The RF receiver front-end of claim 3 , further comprising a configurable input matching network coupled with the LNA block, and wherein the bandwidth and the gain of the RF receiver front-end are adjustable based on a configuration of the input matching network. 5. The RF receiver of claim 4 , wherein i) the configuration states of the configurable input matching network and the configurable output matching network and ii) the bypass state of the selectively bypassable source follower amplifier stage are controlled by a switching network. 6. The RF receiver of claim 5 , wherein the configurable input matching network and the configurable output matching network comprise selectively switchable capacitors and inductors. 7. The RF receiver front-end of claim 6 , wherein the LNA block comprises an amplifying element including a first transistor and a second transistor, the first and the second transistor being arranged in a cascode configuration. 8. The RF receiver front-end of claim 7 , the switchable capacitors comprise a capacitor coupling across a drain-source junction of the first transistor of the amplifying element. 9. The RF receiver front-end of claim 7 , further comprising a feedback resistor coupling a drain terminal of the second transistor of the amplifying element to a gate terminal of the first transistor of the amplifying element. 10. The RF receiver front-end of claim 6 , wherein the inductors comprise a first inductor and a second inductor arranged in series, the second inductor being selectively switchable. 11. The RF receiver front-end of claim 6 , wherein the output matching network further comprises a resistor, the resistor being switched in for a wider bank operation. 12. The RF receiver front-end of claim 5 , wherein the switching network configures and reconfigures the RF receiver front-end to operate at one or more frequency ranges comprising at least a narrowband, an extended narrowband and a wideband frequency range. 13. The RF receiver front-end of claim 1 , implemented on a single die or chip. 14. A method to control an RF receiver front-end including a low noise amplifier (LNA), the method comprising: providing a configurable output matching network; providing a source follower amplifier, and based on a desired gain and/or bandwidth: selectively connecting or disconnecting one of the configurable output matching network or the source follower amplifier to the LNA. 15. The method of claim 14 , further comprising shorting a gate terminal of the source follower amplifier to ground when connecting the output matching network to the LNA.

Assignees

Inventors

Classifications

  • H04B1/18Primary

    Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

  • Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

  • in integrated circuits · CPC title

  • using diplexing or multiplexing filters for selecting the desired band · CPC title

  • Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H) · CPC title

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What does patent US11728837B2 cover?
Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The…
Who is the assignee on this patent?
Psemi Corp
What technology area does this patent fall under?
Primary CPC classification H04B1/18. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 15 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).