Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers

Patent metadata

Field	Value
Publication number	US-9748985-B2
Application number	US-201615234631-A
Country	US
Kind code	B2
Filing date	Aug 11, 2016
Priority date	Apr 24, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

First claim

What is claimed is:

1. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising:
a first operating frequency region implemented in the die structure including a first transmit chain and a first receive chain;
a second operating frequency region implemented in the die structure including a second transmit chain and a second receive chain;
a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain; and
a shared voltage regulator disposed in the shared region of the die structure and connected to the shared power input pad, the shared voltage regulator including a first operating frequency regulated power output connected to the first transmit chain and the first receive chain, and a second operating frequency regulated power output connected to the second transmit chain and the second receive chain.

2. The integrated circuit architecture of claim 1 wherein the first transmit chain includes at least one first operating frequency power amplifier.

3. The integrated circuit architecture of claim 1 wherein the first receive chain includes at least one first operating frequency low noise amplifier.

4. The integrated circuit architecture of claim 1 wherein the second transmit chain includes at least one second operating frequency power amplifier.

5. The integrated circuit architecture of claim 1 wherein the second receive chain includes at least one second operating frequency low noise amplifier.

6. The integrated circuit architecture of claim 1 wherein the shared voltage regulator is a low drop off voltage regulator.

7. The integrated circuit architecture of claim 1 wherein the shared region of the die structure includes a control input conductive pad connected to both the first transmit chain and the second transmit chain.

8. The integrated circuit architecture of claim 1 wherein the shared region of the die structure includes a control input conductive pad connected to both the first receive chain and the second receive chain.

9. The integrated circuit architecture of claim 1 further comprising a co-planar inductor defined by a terminal connected to a one of the plurality of exposed conductive pads, and a conductive trace wound around a periphery of the one of the plurality of exposed conductive pads in a spiral.

10. The integrated circuit architecture of claim 1 further comprising solder balls bonded to each of the exposed conductive pads.

11. The integrated circuit architecture of claim 1 further comprising copper pillars attached to each of the exposed conductive pads.

12. An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising:
a first operating frequency region defined by a first outer periphery and an opposed first inner periphery and implemented in the die structure, the first operating frequency region including a first transmit chain and a first receive chain, a first subset of the plurality of exposed conductive pads corresponding to the first transmit chain and the first receive chain, and the first subset of the plurality of exposed conductive pads including a first antenna conductive pad;
a second operating frequency region defined by a second outer periphery and an opposed second outer periphery and implemented in the die structure, the second operating frequency region including a second transmit chain and a second receive chain, a second subset of the plurality of exposed conductive pads corresponding to the second transmit chain and the second receive chain, and the second subset of the plurality of exposed conductive pads including a second antenna conductive pad; and
a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region, with the first inner periphery of the first operating frequency region and the second inner periphery of the second operating frequency region both being adjacent to the shared region, the shared region including a third subset of the plurality of exposed conductive pads that are in both the first subset and the second subset of the plurality of exposed conductive pads.

13. The integrated circuit architecture of claim 12 wherein the first operating frequency region of the die structure includes a first switch disposed thereon selectively connecting the first antenna conductive pad to the first transmit chain and the first receive chain, and the second operating frequency region of the die structure includes a second switch disposed thereon selectively connecting the second antenna conductive pad to the second transmit chain and the second receive chain.

14. The integrated circuit architecture of claim 12 wherein the first transmit chain includes at least one first operating frequency power amplifier.

15. The integrated circuit architecture of claim 12 wherein the first receive chain includes at least one first operating frequency low noise amplifier.

16. The integrated circuit architecture of claim 12 wherein the second transmit chain includes at least one second operating frequency power amplifier.

17. The integrated circuit architecture of claim 12 wherein the second receive chain includes at least one second operating frequency low noise amplifier.

18. The integrated circuit architecture of claim 12 wherein the third subset of the plurality of exposed conductive pads includes a shared power input conductive pad and a shared power detection output conductive pad.

19. The integrated circuit architecture of claim 18 wherein the shared power input conductive pad is connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain.

20. The integrated circuit architecture of claim 18 wherein the shared power detection output conductive pad is connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain.

21. The integrated circuit architecture of claim 18 further comprising a shared voltage regulator disposed in the shared region of the die structure and connected to the shared power input pad, the shared voltage regulator including a first operating frequency regulated power output connected to the first transmit chain and the first receive chain, and a second operating frequency regulated power output connected to the second transmit chain and the second receive chain.

22. The integrated circuit architecture of claim 12 wherein an arrangement of the first subset of the plurality of exposed conductive pads is mirrored relative to an arrangement of the second subset of the plurality of exposed conductive pads.

Assignees

• Skyworks Solutions Inc

Inventors

• Zhang Lisette L
• Gorbachov Oleksandr

Classifications

• H03F3/24

  of transmitter output stages · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title