Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

Patent metadata

Field	Value
Publication number	US-11728812-B2
Application number	US-202117444771-A
Country	US
Kind code	B2
Filing date	Aug 10, 2021
Priority date	Oct 30, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

First claim

What is claimed is:

1. A method, comprising:
reading operand 6 (OP[6]) of a mode register of one or more dynamic random access memory (DRAM) die or dice in a package;
determining which of the DRAM die or dice in the package is designated as termination impedance (ZQ) Master, wherein the DRAM die or dice designated as ZO Master is determined based at least in part on reading OP[6] of the mode register; and
issuing a ZQ calibration command to the DRAM die or dice designated as ZQ Master in the package.

2. The method of claim 1 , wherein the method is performed when the package is operated in a mode in which a calibration associated with a ZQ occurs in response to a command.

3. The method of claim 2 , wherein the command comprises the ZQ calibration command.

4. The method of claim 1 , wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

5. The method of claim 4 , further comprising:
determining that the DRAM die or dice is not the ZQ Master based at least in part on reading a logic value of 0 at OP[6].

6. The method of claim 4 , further comprising:
determining that the DRAM die or dice is the ZQ Master based at least in part on reading a logic value of 1 at OP[6].

7. The method of claim 4 , wherein a value of OP[6] has a default value of 0 to indicate that one of the DRAM die is not a ZQ Master or is set to a value of 1 to indicate that the DRAM die is a ZQ Master.

8. An apparatus, comprising:
a memory controller configured to determine which dynamic random access memory (DRAM) die or dice in a package comprising one or more DRAM dice is designated as termination impedance (ZQ) Master, read operand 6 (OP[6]) of a mode register of one or more DRAM die or dice in the package, wherein the DRAM die or dice designated as ZO Master is determined based at least in part on reading OP[6] of the mode register, and to issue a ZQ calibration command to the DRAM die or dice designated as ZQ Master in the package.

9. The apparatus of claim 8 , wherein the memory controller reads a mode register comprising eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

10. The apparatus of claim 8 , wherein the memory controller is further configured to determine that the DRAM die or dice is not the ZQ Master based at least in part on reading a logic value of 0 at OP[6].

11. The apparatus of claim 8 , wherein the memory controller is further configured to determine that the DRAM die or dice is the ZQ Master based at least in part on reading a logic value of 1 at OP[6].

12. The apparatus of claim 8 , wherein a value of OP[6] read by the memory controller has a default value of 0 to indicate that one of the DRAM die is not a ZQ Master or has a value of 1 to indicate that the DRAM die is a ZQ Master.

13. The apparatus of claim 8 , wherein the memory controller is further configured to operate the package in a mode in which a calibration associated with a ZQ occurs in response to a command.

14. A method, comprising:
operating in a mode in which calibration associated with a termination impedance (ZQ) occurs in response to a command;
receiving a ZQ calibration command at a dynamic random access (DRAM) die or dice designated as ZQ Master in a package comprising one or more DRAM dice; and
storing information at operand 6 (OP[6]) of a mode register of one or more DRAM die or dice in the package, wherein the DRAM die or dice designated as ZO Master is identified based at least in part on OP[6] of the mode register.

15. The method of claim 14 , wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]), and OP[6] comprises an indication of ZQ Master.

16. The method of claim 14 , wherein the DRAM die or dice not designated as the ZQ Master is based at least in part on a logic value of 0 stored at OP[6].

17. The method of claim 14 , wherein the DRAM die or dice is designated the ZQ Master based at least in part on a logic value of 1 stored at OP[6].

Assignees

• Micron Technology Inc

Inventors

• Gans Dean

Classifications

• H03K19/018585 Primary

  programmable · CPC title

• G06F13/4086

  Bus impedance matching, e.g. termination · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C29/022

  in I/O circuitry · CPC title