Maintenance operations in a DRAM

Patent metadata

Field	Value
Publication number	US-9318183-B2
Application number	US-201514937788-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Jan 22, 2009
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

First claim

What is claimed is:

1. A method of operating a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
receiving a self-refresh command from a memory controller;
responsive to the self-refresh command, during a first time interval, performing a self-refresh operation to refresh data stored in at least one bank of the plurality of memory banks;
receiving an operation code from the memory controller, the operation code specifying a calibration operation; and
in response to receiving the operation code, performing a calibration operation of the command interface during at least a portion of the first interval.

2. The method of claim 1 , including, in response to receiving the operation code, configuring the command interface of the memory device to operate in the calibration mode.

3. The method of claim 1 , wherein configuring the command interface of the memory device to operate in the calibration mode includes placing the command interface of the memory device into a loopback mode.

4. The method of claim 1 , wherein, in the loopback mode, respective pairs of data links of the command interface are linked to form loopback paths, and respective pairs of command/address links of the command interface are linked to form loopback paths.

5. The method of claim 1 , wherein the operation code received from the memory controller comprises a sub-operation code of the self-refresh command received from the memory controller.

6. The method of claim 1 , further comprising, while a calibration of the command interface is being performed, concurrently receiving information from the memory controller on a first data path and transmitting data to the memory controller on a second data path.

7. The method of claim 6 , wherein performing the calibration of the command interface of the memory device includes performing a timing calibration.

8. The method of claim 7 , wherein performing the timing calibration comprises:
receiving from the memory controller, at the command interface of the memory device, a pattern on the first data path; and
transmitting from the command interface of the memory device to the memory controller the pattern on the second data path.

9. The method of claim 1 , wherein the self-refresh command specifies a bank order for the plurality of memory banks, and wherein responsive to the self-refresh command, the memory device sequentially refreshes a respective row in the plurality of memory banks, in the specified bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the self-refresh command.

10. The method of claim 1 , wherein the self-refresh command specifies a bank order for the plurality of memory banks, and wherein responsive to the self-refresh command, the memory device sequentially refreshes a respective row in the plurality of memory banks, in the specified bank order, wherein the self-refresh command includes a first value specifying a first memory bank that is to be refreshed first in response to the self-refresh command and a second value specifying a second bank that is to be refreshed second in response to the self-refresh command.

11. A memory device comprising:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
a command interface operable to accept commands from a memory controller;
refresh circuitry configured to perform a self-refresh operation to refresh data stored in at least one bank of the plurality of memory banks in response to a self-refresh command from the memory controller; and
control logic to configure the enable the command interface to enter a calibration mode while the refresh circuitry performs the self-refresh operation;
wherein
in the calibration mode, the command interface is configured to perform a respective calibration operation, of a plurality of calibration operations, in accordance with an operation code received from the memory controller.

12. The memory device of claim 11 , wherein
the command interface includes a first signaling path and a second signaling path; and
in the calibration mode, the command interface is configured to concurrently receive information from the memory controller on the first signaling path and transmits data to the memory controller on the second signaling path.

13. The memory device of claim 11 , wherein the command interface is configured to be placed into a loopback mode while the command interface is in the calibration mode.

14. The memory device of claim 11 , wherein the command interface is configured to enter a calibration mode while the refresh circuitry performs the self-refresh operation.

15. The memory device of claim 11 , wherein the command interface is configured to enter a calibration mode, in response to receiving an operation code from the memory controller, while the refresh circuitry performs the self-refresh operation.

16. The memory device of claim 15 , wherein the operation code received from the memory controller comprises a sub-operation code of the self-refresh command received from the memory controller.

17. The memory device of claim 11 , wherein the command interface is configured to concurrently receive information from the memory controller on a first data path and transmit data to the memory controller on a second data path.

18. The memory device of claim 17 , wherein the command interface is configured to receive a pattern on the first data path and to transmit the pattern on the second data path.

19. The memory device of claim 11 , wherein the self-refresh command specifies a bank order for the plurality of memory banks, and wherein the refresh circuitry in configured to sequentially refresh, in response to the self-refresh command, a respective row in the plurality of memory banks, in the specified bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the self-refresh command.

20. A memory device comprising:
a plurality of memory banks, each bank including a plurality of rows of memory cells;
interface means for accepting commands from a memory controller;
refresh means configured to perform a self-refresh operation to refresh data stored in at least one bank of the plurality of memory banks in response to a self-refresh command from the memory controller; and
logic means to configure the enable the command interface to enter a calibration mode while the refresh circuitry performs the self-refresh operation;
wherein
in the calibration mode, the interface means is configured to perform a respective calibration operation, of a plurality of calibration operations, in accordance with an operation code received from the memory controller.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W

Classifications

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06Q20/00

  Payment architectures, schemes or protocols (apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12) · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title