Semiconductor device and method for adjusting impedance of output circuit

Patent metadata

Field	Value
Publication number	US-9294072-B2
Application number	US-201414331070-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Jul 16, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an impedance adjustment circuit that generates a plurality of first impedance adjustment signals, a second impedance adjustment signal, and a third impedance adjustment signal and comprises a counter circuit outputting a count value thereof as the plurality of first impedance adjustment signals, a mode selection circuit setting the second impedance adjustment signal to be in an active state or in an inactive state irrespective of the count value of the counter circuit, and a level fixing circuit fixing the third impedance adjustment signal to be in an active state;
a pre-stage circuit that generates a plurality of first output control signals in response to a data signal and the plurality of first impedance adjustment signals, generates a second output control signal in response to the data signal and the second impedance adjustment signal, and generates a third output control signal in response to the data signal and the third impedance adjustment signal;
a first power supply wiring;
an output terminal; and
an output circuit that comprises a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between the output terminal and the first power supply wiring, the plurality of first transistors being configured to receive the plurality of first output control signals via control terminals of the first transistors, respectively, the second transistor being configured to receive the second output control signal via a control terminal of the second transistor, and the third transistor being configured to receive the third output control signal via a control terminal of the third transistor.

2. The semiconductor device according to claim 1 ;
wherein on-resistance of the second transistor is smaller than on-resistances of the plurality of first transistors.

3. The semiconductor device according to claim 1 , further comprising:
a replica circuit that comprises a plurality of fourth transistors, a fifth transistor, and a sixth transistor corresponding to the plurality of first transistors, the second transistor, and the third transistor in the output circuit, respectively, and being connected in parallel to each other;
wherein the counter circuit, the mode selection circuit, and the level fixing circuit control the plurality of fourth transistors, the fifth transistor, and the sixth transistor on the basis of the plurality of first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, to adjust a replica impedance of the replica circuit.

4. The semiconductor device according to claim 3 ;
wherein on-resistance of the fifth transistor is smaller than on-resistances of the plurality of fourth transistors.

5. The semiconductor device according to claim 3 ;
wherein, in a predetermined determination period, the impedance adjustment circuit compares the replica impedance with a desired value while controlling the plurality of first impedance adjustment signals and the third impedance adjustment signal to be in an active state and the second impedance adjustment signal to be in an inactive state; and
wherein, after the predetermined determination period, the mode selection circuit in the impedance adjustment circuit sets the second impedance adjustment signal on the basis of a result of the comparison.

6. The semiconductor device according to claim 5 ;
wherein, if the result of the comparison indicates that the replica impedance is larger than the desired value, the mode selection circuit in the impedance adjustment circuit sets the second impedance adjustment signal to be in an active state after the predetermined determination period and if the result of the comparison indicates that the replica impedance is smaller than the desired value, the mode selection circuit in the impedance adjustment circuit sets the second impedance adjustment signal to be in an inactive state after the predetermined determination period.

7. The semiconductor device according to claim 5 ;
wherein the mode selection circuit generates a determination mode end signal indicating that the predetermined determination period is ended; and
wherein the impedance adjustment circuit starts adjustment of the replica impedance by using the plurality of first impedance adjustment signals outputted by the counter circuit in response to the determination mode end signal.

8. The semiconductor device according to claim 5 , comprising:
an external resistor that has an impedance corresponding to the desired value;
a first terminal that is connected to one end of the replica circuit and one end of the external resistor; and
a comparison circuit that comprises two input nodes, one of which being connected to the first terminal and the other of which being supplied with a reference voltage;
wherein the comparison circuit outputs the result of the comparison.

9. The semiconductor device according to claim 5 , comprising:
a second replica circuit that has an impedance adjusted to correspond to the desired value;
a first node that is connected to one end of the replica circuit and one end of the second replica circuit; and
a comparison circuit that comprises two input nodes, one of which being connected to the first node and the other of which being supplied with a reference voltage;
wherein the comparison circuit outputs the result of the comparison.

10. An output circuit impedance adjustment method for adjusting an impedance of an output circuit comprising a plurality of transistors connected in parallel to each other, the method comprising:
comparing a replica impedance of a replica circuit having a same configuration as that of the plurality of transistors connected in parallel to each other in the output circuit with a desired value while controlling one of the plurality of transistors in the replica circuit to be off as an initial adjustment transistor and transistors other than the initial adjustment transistor to be on in a predetermined determination period;
setting, if a result of the comparison indicates that the replica impedance is larger than the desired value, the initial adjustment transistor to on and adjusting the replica impedance by using the transistors other than the initial adjustment transistor after the predetermined determination period;
setting, if a result of the comparison indicates that the replica impedance is smaller than the desired value, the initial adjustment transistor to off and adjusting the replica impedance by using the transistors other than the initial adjustment transistor after the predetermined determination period; and
setting on/off of the plurality of transistors in the output circuit on the basis of a result of the adjustment of the replica impedance.

Assignees

• Micron Technology Inc

Inventors

• Kaneko Yuhei
• Nakamura Kohei

Classifications

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03H7/38

  Impedance-matching networks · CPC title

• H03H11/28 Primary

  Impedance matching networks · CPC title