Semiconductor die orifices containing metallic nanowires

Patent metadata

Field	Value
Publication number	US-11728242-B2
Application number	US-202016843618-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	Apr 8, 2019
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor die having a first surface and a second surface opposing the first surface;
an orifice extending through a thickness of the semiconductor die from the first surface to the second surface;
a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface; and
a metal layer on the first surface of the semiconductor die, one end of the metallic nanowires are fused to the metal layer.

2. A semiconductor package, comprising:
a semiconductor die having a first surface and a second surface opposing the first surface;
an orifice extending through a thickness of the semiconductor die from the first surface to the second surface;
a first metal layer on the first surface;
a second metal layer on the second surface;
a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first metal layer to the second metal layer, one end of each of the metallic nanowires is fused to the first metal layer and a second end of each of the metallic nanowires is plated to the second metal layer; and
a second semiconductor die on the second metal layer.

3. The semiconductor package of claim 2 , wherein the second metal layer comprises a set of nanoparticles.

4. The semiconductor package of claim 2 , further comprising a set of nanoparticles positioned on the second metal layer and within the orifice, the set of metallic nanowires are plated to the set of nanoparticles.

5. The semiconductor package of claim 4 , wherein a nanoparticle in the set of nanoparticles has a diameter ranging from 0.01 microns to 1.50 microns.

6. The semiconductor package of claim 2 , wherein a nanowire in the set of metallic nanowires have a length-to-diameter ratio of at least 2:1.

7. The semiconductor package of claim 2 , wherein the orifice has a diameter ranging from 0.1 microns to 2 millimeters.

8. The semiconductor package of claim 2 , wherein a nanowire in the set of metallic nanowires has a diameter ranging from 5 nanometers to 100 microns and a length ranging from 10 microns to 1000 microns.

9. A semiconductor package, comprising:
a first semiconductor die having a first surface and a second surface opposing the first surface, an orifice extending through the first semiconductor die from the first surface to the second surface;
a first metal layer positioned on the first surface;
a second metal layer positioned on the second surface;
a set of metallic nanowires positioned inside the orifice and coupled to the first and second metal layers, wherein a first end of each of the metallic nanowires is fused to the first metal layer and a second end of each of the metallic nanowires is plated to the second metal layer; and
a second semiconductor die coupled to the second metal layer.

10. The semiconductor package of claim 9 , wherein the second metal layer comprises a set of nanoparticles, the set of metallic nanowires extending from the set of nanoparticles.

11. The semiconductor package of claim 9 , further comprising a set of nanoparticles positioned on the second metal layer and within the orifice, the set of metallic nanowires extending from the set of nanoparticles.

12. The semiconductor package of claim 11 , wherein a nanowire in the set of metallic nanowires has a diameter ranging from 5 nanometers to 100 microns, and wherein the nanowire has a length ranging from 10 microns to 1000 microns.

13. The semiconductor package of claim 9 , wherein the orifice has a diameter ranging from 0.1 microns to 2 millimeters.

14. A method, comprising:
positioning a first metal layer on a first surface of a first semiconductor die, the first semiconductor die having a second surface opposite the first surface;
etching an orifice in the first semiconductor die, the orifice extending through a thickness of the first semiconductor die between the first and second surfaces;
positioning a second metal layer on a surface of a second semiconductor die;
positioning a set of nanoparticles on the second metal layer;
plating a set of metallic nanowires on the set of nanoparticles;
positioning the set of metallic nanowires and second nanoparticles in the orifice; and
fusing ends of the metallic nanowires, not plated to the nanoparticles, to the first metal layer.

15. The method of claim 14 , wherein plating the set of metallic nanowires on the set of nanoparticles comprises using a nanowire template having a plurality of orifices, plating material filling the orifices, in the nanowire template having a diameter less than 100 microns.

16. The method of claim 14 , wherein the orifices have a diameter ranging from 0.1 microns to 2 millimeters.

17. The method of claim 14 , wherein a nanowire in the set of metallic nanowires has a length-to-diameter ratio of at least 10:1.

18. The method of claim 14 , wherein a nanoparticle in the set of nanoparticles has a diameter of less than 1.5 microns.

19. The method of claim 14 , wherein the nanowires are directly connected to the first metal layer.

20. A method, comprising:
positioning a first metal layer on a first surface of a first semiconductor die, the first semiconductor die having a second surface opposite the first surface;
etching an orifice in the first semiconductor die, the orifice extending through a thickness of the first semiconductor between the first and second surfaces;
positioning a first metal layer on a first surface of a second semiconductor die, the second semiconductor die having a second surface opposite the first surface;
positioning a set of nanoparticles on a side of the first metal layer on the first surface of the second semiconductor die facing away from the second semiconductor die;
plating a set of metallic nanowires on the set of nanoparticles in the orifice; and
fusing an end of the metallic nanowires not attached to the set of nanoparticles to the first metal layer on a first surface of the first semiconductor die.

21. The method of claim 20 , wherein plating the set of metallic nanowires on the set of nanoparticles comprises using a nanowire template having a plurality of orifices, an orifice in the nanowire template having a diameter less than 100 microns.

22. The method of claim 20 , wherein the orifice has a diameter ranging from 0.1 microns to 2 millimeters.

23. The method of claim 20 , wherein a nanowire in the set of metallic nanowires has a length-to-diameter ratio of at least 10:1.

24. The method of claim 20 , wherein a nanoparticle in the set of nanoparticles has a diameter of less than 1.5 microns.

25. The method of claim 20 , wherein the nanowires are directly connected to the second metal layer.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Muenster Ralf Jakobskrueger
• Koduri Sreenivasan Kalyani

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W72/30

  Die-attach connectors · CPC title