Dynamic valley searching in solid state drives

Patent metadata

Field	Value
Publication number	US-11727996-B2
Application number	US-202217961468-A
Country	US
Kind code	B2
Filing date	Oct 6, 2022
Priority date	Mar 10, 2021
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

First claim

What is claimed is:

1. A method of utilizing dynamic valley searches, the method comprising:
writing data to a plurality of planes of a storage device utilizing a multi-pass programming process wherein;
an initial searching read during an intermediate stage of the multi-pass programming process is utilized; and
a series of valley scans is performed to verify the data; and
reading the stored data utilizing a calibrated read derived from an initial searching read comprising at least a series of valley scans performed on planes within the plurality of planes.

2. The method of claim 1 , wherein the calibrated read utilizes calibration data.

3. The method of claim 2 , wherein the calibrated read utilizes calibration data generated from at least two searching reads and threshold valley scans.

4. The method of claim 3 , wherein each of the at least two searching reads and threshold valley scans is performed on unique planes of the plurality of planes.

5. The method of claim 4 , wherein the calibration data is based on the at the least two searching reads and threshold valley scans.

6. The method of claim 5 , wherein the searching read and threshold valley scan performed on each plane of the plurality of planes utilizes a unique memory state.

7. The method of claim 6 , wherein each of the searching reads and threshold valley scans performed on each plane of the plurality of plane generates calibration data associated with the unique memory state.

8. The method of claim 7 , wherein the generated calibration data is pooled together for each memory state for use as calibration data across all planes within the plurality of planes.

9. A method of utilizing dynamic valley searches, the method comprising:
writing data to a plurality of planes of a storage device utilizing a multi-pass programming process wherein;
calibration data is generated utilizing:
a searching read is conducted over a plurality of threshold levels during an intermediate stage of the multi-pass programming process; and
a series of valley scans is performed to verify the data; and

reading the stored data via a calibrated read utilizing the previously generated calibration data.

10. The method of claim 9 , wherein the searching read comprises at least a series of threshold valley scans on each of the plurality of planes.

11. The method of claim 9 , wherein the searching read is conducted over a plurality of threshold levels.

12. The method of claim 11 , wherein a valley scan is performed at each of the plurality of threshold levels.

13. The method of claim 9 , wherein the calibrated read is performed on a word line.

14. The method of claim 13 , wherein each word line associated with the data write undergoes a calibrated read.

15. The method of claim 9 , wherein a plurality of memory states are selected within each plane of the plurality of planes.

16. The method of claim 15 , wherein a calibrated read is performed on each of the selected plurality of memory states.

17. The method of claim 16 , wherein a memory state from the selected plurality of memory states is assigned to a particular plane of the plurality of planes.

18. The method of claim 17 , wherein the assigning of the memory states is configured such that each plane of the plurality of planes is assigned a unique memory state from the plurality of selected memory states.

19. A storage device, comprising:
a controller configured to direct the storage device to:
perform an initial searching read associated with data that necessitates access to multiple planes of memory simultaneously, wherein:
a plurality of memory states for calibration are determined;
a plurality of threshold valleys between the memory states are determined;
a series of searching reads and valley scans are performed on the plurality of planes; and
generate calibration data based on the initial searching reads.

20. The storage device of claim 19 , wherein a memory state is assigned to each of the plurality of planes for performing searching reads.

Assignees

• Western Digital Tech Inc

Inventors

• Singidi Harish
• Banerjee Amiya
• Gupta Shantanu

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title