On chip dynamic read level scan and error detection for nonvolatile storage

Patent metadata

Field	Value
Publication number	US-9710325-B2
Application number	US-201514681800-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Sep 6, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

First claim

What is claimed is:

1. A method of operating non-volatile storage, comprising:
a) reading a first unit of data stored in a group of non-volatile storage elements on a memory die using a plurality of different read levels;
b) storing results of reads at the two most recent different read levels on the memory die;
c) determining a count of how many of the non-volatile storage elements in the group showed a different result between the reads at the two most recent read levels;
d) determining whether a minimum of the count is greater than a threshold number;
e) storing the first unit of data in a data latches on the memory die without applying error correction if the minimum count is less than or equal to the threshold number;
f) storing the first unit of data in the data latches on the memory die with applying error correction if the minimum count is greater than the threshold number, including:
reading the unit of data and error correction codes associated with the unit of data;
using the error correction codes to correct misreads to generate corrected data; and
storing the corrected data into the data latches.

2. The method of claim 1 , wherein the first unit of data is a first page of data, the data latches are a first set of data latches, and further comprising:
storing a second page of data into a second set of data latches; and
programming the second page of data into the group of non-volatile storage elements, the programming is based on the first page of data that is stored in the first set of data latches.

3. The method of claim 1 , wherein the data latches are a first set of data latches, and further comprising:
repeating said a) through said f) to store a second unit of data into a second set of data latches;
programming the first unit of data and the second unit of data into a second group of non-volatile storage elements as multiple bits per storage element.

4. The method of claim 3 , further comprising:
establishing a default read level for reading based on one of the read levels that was used when the count reached the minimum.

5. The method of claim 1 , further comprising:
instructing a memory controller to correct for misreads in response to determining that the count is greater than the threshold number.

6. The method of claim 1 , wherein the storing results of reads at the two most recent different read levels on the memory die includes storing results from reading at a first of the read levels in a first data latch and storing results from reading at a second of the read levels in a second data latch, the determining a count of how many of the non-volatile storage elements in the group showed a different result between the reads at the two most recent read levels includes performing an XOR of the results in the first data latch with the results in the second data latch.

7. The method of claim 1 , wherein the non-volatile storage elements are part of a three-dimensional memory array.

8. A non-volatile storage device, comprising:
a memory die;
a plurality of non-volatile storage elements on the memory die;
a plurality of data latches on the memory die; and
one or more managing circuits in communication with the plurality of non-volatile storage elements and the plurality of data latches, the one or more managing circuits read a first unit of data stored in a group of the plurality of non-volatile storage elements using a plurality of different read levels, the one or more managing circuits store results of reads at the two most recent different read levels in a group of the plurality of data latches, the one or more managing circuits determine a count of how many of the non-volatile storage elements in the group showed a different result between the reads at the two most recent read levels, the one or more managing circuits determine when the count reaches a minimum, the one or more managing circuits determine whether the minimum count is greater than a threshold number when the count reaches the minimum, the one or more managing circuits store the first unit of data in a set of data latches of the plurality of data latches without applying error correction if the minimum count is less than or equal to the threshold number, the one or more managing circuits read the unit of data and error correction codes associated with the unit of data if the minimum count is greater than the threshold number, the one or more managing circuits use the error correction codes to correct misreads to generate corrected data if the minimum count is greater than the threshold number, the one or more managing circuits store the corrected data into the set of data latches if the minimum count is greater than the threshold number.

9. The non-volatile storage device of claim 8 , wherein the plurality of non-volatile storage elements are arranged as NAND strings.

10. The non-volatile storage device of claim 8 , wherein the one or more managing circuits perform a programming operation based on the data stored in the set of data latches.

11. The non-volatile storage device of claim 8 , wherein the first unit of data is a first page of data, the set of data latches is a first set of data latches, and wherein the one or more managing circuits:
store a second page of data into a second set of data latches of the plurality of data latches; and
program the second page of data into the group of non-volatile storage element based on the first page of data that is stored in the first set of data latches.

12. The non-volatile storage device of claim 8 , wherein the set of data latches is a first set of data latches, and wherein the one or more managing circuits:
store a second unit of data into a second set of data latches of the plurality of data latches;
program the first unit of data and the second unit of data into a second group of non-volatile storage elements as multiple bits per storage element.

13. The non-volatile storage device of claim 8 , wherein the one or more managing circuits:
establish a default read level for reading based on one of the read levels that was used when the count reached the minimum.

14. The non-volatile storage device of claim 8 , further comprising a memory controller in communication with the memory die;
wherein the one or more managing circuits instructs the memory controller to correct for misreads in response to the one or more managing circuits determining that the count is greater than the threshold number.

15. The non-volatile storage device of claim 8 , further comprising an XOR circuit on the memory die and coupled to the plurality of data latches;
wherein when the one or more managing circuits store the results of the reads at the two most recent different read levels on the memory die the one or more managing circuits store results from reading at a first of the read levels in a first data latch and store results from reading at a second of the read levels in a second data latch;
wherein when the one or more managing circuits determine a count of how many of the non-volatile storage elements in the group showed a different result between the reads at the two most recent read levels the one or more managing circuits cause the XOR circuit to perform an XOR of the results in the first data latch with the results in the second data latch.

16. A non-volatile storage device, comprising:
a memory die comprising a three-dimensional memory array and a plurality of data latches, wherein the three-dimensional memory array comprises a plurality of non-volatile storage elements; and
a managing circuit in communication with the plurality of non-volat

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Chen Wenzhou
• Zhou Zhenming
• Wan Jun
• Dutta Deepanshu
• Chen Yi-Chieh
• Lee Dana

Classifications

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title