Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETs

Patent metadata

Field	Value
Publication number	US-11727258-B2
Application number	US-202217939807-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Jul 5, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

First claim

What is claimed is:

1. A neuromorphic multi-bit digital weight cell configured to store a plurality of potential weights for a neuron in an artificial neural network, the neuromorphic multi-bit digital weight cell comprising:
a parallel cell comprising:
a plurality of passive resistors in parallel; and
a plurality of gating transistors, each gating transistor of the plurality of gating transistors being in series with one passive resistor of the plurality of passive resistors;

a plurality of programming input lines connected to the plurality of gating transistors;
an input terminal connected to the parallel cell; and
an output terminal connected to the parallel cell,
wherein at least one passive resistor of the plurality of passive resistors comprises an un-gated FinFET having an n-doped channel and n+ doped source and drain regions.

2. The neuromorphic weight cell of claim 1 , wherein a first passive resistor of the plurality of passive resistors has a first resistance and a second passive resistor of the plurality of passive resistors has a second resistance, the second resistance being half the first resistance.

3. The neuromorphic weight cell of claim 2 , wherein a third passive resistor of the plurality of passive resistors has a third resistance, the third resistance being half the second resistance.

4. The neuromorphic weight cell of claim 1 , wherein the neuromorphic weight cell has a total conductance defined by G tot =Σ i=0 b i 2 i G 0 , where b i is a Boolean value of bit i and G 0 is a smallest conductance in the neuromorphic weight cell.

5. The neuromorphic weight cell of claim 1 , wherein neuromorphic weight cell is configured to generate a plurality of potential conductances uniformly distributed, and wherein the potential weights are proportional to the potential conductances.

6. The neuromorphic weight cell of claim 1 , wherein a doping concentration of the ungated FinFET is between approximately 10 18 cm −3 and approximately 10 19 cm −3 , and wherein the un-gated FinFETs is doped with As or P doping.

7. The neuromorphic weight cell of claim 1 , wherein a channel length of the un-gated FinFET is approximately 30 nm, and wherein a doping concentration of the un-gated FinFET is approximately 6*10 18 cm −3 .

8. The neuromorphic weight cell of claim 1 , wherein an overall length of the un-gated FinFET spans more than one contacted poly pitch (CPP).

9. The neuromorphic weight cell of claim 8 , wherein the at least one passive resistor of the plurality of passive resistors comprises a plurality of un-gated FinFETs.

10. The neuromorphic weight cell of claim 1 , wherein each gating transistor of the plurality of gating transistors is a standard core logic transistor.

11. The neuromorphic weight cell of claim 10 , wherein the standard core logic transistor is a FinFET or a gate-all-around field effect transistor (GAA FET).

12. The neuromorphic weight cell of claim 1 , wherein each gating transistor of the plurality of gating transistors is a ferroelectric FET (FeFET), the FeFET comprising a ferroelectric capacitor (FeCap) and an underlying FET, wherein the FeCap is connected to a gate of the underlying FET.

13. The neuromorphic weight cell of claim 12 , wherein the FeCap comprises a pair of titanium nitride (TiN) electrodes and a hafnium zirconium oxide (HfZrO 2 ) ferroelectric layer between the pair of TiN electrodes.

14. The neuromorphic weight cell of claim 12 , wherein the FeCap of each FeFET is at a metal layer in a back-end-of-line of the neuromorphic weight cell.

15. The neuromorphic weight cell of claim 14 , wherein the metal layer is lowermost metal routing layer M0.

16. The neuromorphic weight cell of claim 12 , wherein the FeCap of each FeFET is at an insulating layer in a back-end-of-line of the neuromorphic weight cell.

17. The neuromorphic weight cell of claim 16 , wherein the insulating layer is lowermost insulating layer V0.

18. The neuromorphic weight cell of claim 1 , further comprising:
a selector line connected to the plurality of programming input lines; and
a plurality of selector transistors at junctions between the selector line and the plurality of programming input lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Obradovic Borna J
• Rakshit Titash
• Sengupta Rwik
• Hong Joon Goo
• Hatcher Ryan M
• Kittl Jorge A
• Rodder Mark S

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• G06N3/063 Primary

  using electronic means · CPC title