On-chip dual-supply multi-mode CMOS regulators

Patent metadata

Field	Value
Publication number	US-11726513-B2
Application number	US-202117443093-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	May 30, 2014
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

First claim

What is claimed is:

1. A regulator circuit, comprising:
a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS);
a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS), wherein the second voltage regulator comprises a two-stage Operational Transconductance Amplifier (OTA) circuit, and wherein the first voltage regulator is connected to the second voltage regulator; and
a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator.

2. The regulator circuit of claim 1 , wherein the two-stage OTA circuit provides pole cancellation.

3. The regulator circuit of claim 2 , wherein the two-stage OTA circuit comprises:
a first amplifier;
a second amplifier, wherein an output of the first amplifier is connected to an input of the second amplifier; and
a compensation network connected to a source of the NMOS.

4. The regulator circuit of claim 3 , wherein the compensation network is tunable.

5. The regulator circuit of claim 4 , wherein the compensation network comprises:
a capacitor; and
a resistor in series with the capacitor.

6. The regulator circuit of claim 5 , wherein the output of the first amplifier is connected to a first end of the capacitor, a second end of the capacitor is connected to a first end of the resistor, and wherein a second end of the resistor is connected to the source of the NMOS.

7. The regulator circuit of claim 1 , wherein the first voltage regulator and the second voltage regulator are connected in series.

8. The regulator circuit of claim 7 , wherein a drain of the PMOS is coupled to a drain of the NMOS.

9. The regulator circuit of claim 1 , wherein the first voltage regulator and the second voltage regulator are connected in parallel.

10. The regulator circuit of claim 1 , wherein the first voltage regulator and the second voltage regulator are tunable to change a degree of input voltage regulation.

11. The regulator circuit of claim 1 , wherein the first voltage regulator and the second voltage regulator have different input impedance and output impedance.

12. The regulator circuit of claim 1 , wherein the first voltage regulator comprises a 1-stage operational transconductance amplifier (OTA).

13. The regulator circuit of claim 1 , wherein the switch circuit is programmable to select either i) both the first voltage regulator and the second voltage regulator or ii) one of the first voltage regulator and the second voltage regulator and bypass the other of the first voltage regulator and the second voltage regulator.

14. The regulator circuit of claim 1 , wherein the regulator circuit is adapted to select one of the first voltage regulator or the second voltage regulator based on at least one of a noise bandwidth or a Power Supply Rejection Ratio (PSRR) wherein in particular the second voltage regulator provides for better PSRR than the first voltage regulator.

15. The regulator circuit of claim 1 , further comprising a Voltage Controlled Oscillator (VCO), and wherein the regulator circuit is configured to regulate a supply voltage to the VCO.

16. The regulator circuit of claim 15 , wherein the regulator circuit is adapted to select the supply voltage of the regulator circuit based on a frequency of the VCO.

17. The regulator circuit of claim 15 , wherein the regulator circuit is adapted to select the supply voltage of the regulator circuit based on a power consumption of the VCO.

Assignees

• Qualcomm Inc

Inventors

• Lo Yung-Chung
• Zhang Gang
• Han Yiping
• Bossu Frederic
• Hung Tsai-Pi
• Chang Jae-Hong

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/0077

  Plural converter units whose outputs are connected in series · CPC title