Method and apparatus reduced switch-on rate low dropout regulator (LDO) bias and compensation

Patent metadata

Field	Value
Publication number	US-9235225-B2
Application number	US-201313788115-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	Nov 6, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

First claim

What is claimed is:

1. A reduced switch-on slew low dropout (LDO) regulator, further comprising:
a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;
a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;
a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;
a switchable tail current source, coupled to the controllable slew differential amplifier, configured as switchable between sourcing a slew-limiting bias current and sourcing a full-slew bias current, and comprising a switchable full-slew bias current source and a slew-limiting bias current source, the switchable full-slew bias current source being configured to source the full-slew bias current when ON, the slew-limiting bias current source being in parallel with the switchable full-slew bias current source and configured to source the slew-limiting bias current; and
a tail current control circuit, configured to switch OFF the switchable full-slew bias current source in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition of ST_ON/OFF, to switch ON the switchable full-slew bias current source.

2. The reduced switch-on slew LDO regulator of claim 1 , wherein the LDO regulator is configured to generate the pass gate control signal at the full-slew rate when biasing a transistor with the full-slew bias current, and at the reduced slew rate when biasing the transistor with the slew-limiting bias current.

3. A The reduced switch-on slew low-dropout (LDO) regulator, further comprising
a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;
a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;
a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;
a switchable tail current source, coupled to the controllable slew differential amplifier, and configured as switchable between sourcing a slew-limiting bias current and sourcing a full-slew bias current; and
a tail current control circuit, configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay (DLY) after an OFF-to-ON transition of ST_ON/OFF, to switch the switchable tail current source from the slew-limiting bias current to the full-slew bias current.

4. The reduced switch-on slew LDO regulator of claim 3 , wherein the controllable slew differential amplifier is further configured to slew, in response to the OFF-to-ON transition of ST_ON/OFF, from an initial zero voltage to approximately Vref, at a slew rate slewing from the initial zero voltage to approximately Vref in a time duration approximately equal to DLY.

5. The reduced switch-on slew LDO regulator of claim 4 , wherein the tail current control circuit includes a delay capacitor, and a charging circuit, the charging circuit being configured to charge the delay capacitor in response to the OFF-to-ON transition of ST_ON/OFF, from a zero voltage to a tail current source mode switch threshold, in a charging time having a duration approximately equal to DLY.

6. The reduced switch-on slew LDO regulator of claim 5 , wherein the charging circuit includes a trigger switch, the trigger switch being coupled to a charging current source.

7. A reduced switch-on slew low-dropout (LDO) regulator, further comprising:
a pass gate, configured to controllably couple a voltage rail to a regulator output, the control being based in part on a pass gate control signal;
a controllable slew differential amplifier, switchable between a slew-limiting state and a full-slew state, the controllable slew differential amplifier being configured to receive a feedback from the regulator output, and to generate the pass gate control signal, based on a reference voltage and the feedback, at a full-slew rate in the full-slew state, and at a reduced slew rate in the slew-limiting state;
a pass gate disabling circuit, configured to selectively over-ride the pass gate control signal and switch the pass gate OFF;
a pass gate control line, the pass gate control line being configured to carry the pass gate control signal to a control gate of the pass gate, the pass gate disabling circuit comprising a two-position switch, the two-position switch having a disabling position and an operational position;
a feedback element, coupled to the regulator output and to an input of the controllable slew differential amplifier, in a configuration to provide said feedback; and
a compensation network, configured to couple the pass gate control line to the feedback element, the compensation network having a compensation capacitor and a compensation resistor,
the pass gate disabling circuit being further configured to charge the compensation capacitor when the two-position switch is in the disabling position, and to allow the compensation capacitor to discharge the pass gate control line, to a voltage at which the pass gate is operational, in response to switching the two-position switch from the disabling position to the operational position, and
the disabling position providing a short of the control gate to a voltage disabling the pass gate, and the operational position not providing the short of the control gate, the two-position switch being configured to switch between the disabling position and the operational position based on an ON-OFF state of ST_OFF/ON.

8. The reduced switch-on slew LDO regulator of claim 7 , wherein a rate of the reduced slew rate is based, at least in part, on at least one of a capacitance of the compensation capacitor or a resistance of the compensation resistor, or both.

9. The reduced switch-on slew LDO regulator of claim 8 , wherein the controllable slew differential amplifier includes a switchable tail current source, the switchable tail current source being configured as switchable between sourcing a slew-limiting bias current and a full-slew bias current,
the controllable slew differential amplifier being configured to generate the pass gate control signal at the full-slew rate with the full-slew bias current, and at the reduced slew rate with the slew-limiting bias current, and
the rate of the reduced slew rate being further based, at least in part, on the slew-limiting bias current and at least one of the capacitance of the compensation capacitor or the resistance of the compensation resistor, or both.

10. The reduced switch-on slew LDO regulator of claim 9 , further comprising a tail current control circuit, the tail current control circuit being configured to switch the switchable tail current source to the slew-limiting bias current in response to an ON-to-OFF transition of a system ON-OFF signal (ST_ON/OFF) and, at a delay DLY after an OFF-to-ON transition

Assignees

• Qualcomm Inc

Inventors

• Price Burt L
• Kolla Yeshwant Nagaraj
• Shah Dhaval R

Classifications

• H04N25/779

  Circuitry for scanning or addressing the pixel array · CPC title

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title