Power supply circuit

Patent metadata

Field	Value
Publication number	US-9853540-B2
Application number	US-201314023858-A
Country	US
Kind code	B2
Filing date	Sep 11, 2013
Priority date	Sep 28, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A power supply circuit is intended to suppress power consumption when a load is not driven and to shorten a required time to be taken until a boosted voltage to be supplied to a high-side MOS transistor is stabilized when the load is changed from a deactivated state to an activated state.
The power supply circuit (power supply circuit 3 ) supplying power to a load driving circuit (motor driving circuit 2 ) that drives a load by controlling a high-side MOS transistor M 1 on the basis of an input load control signal includes a booster circuit (charge pump 23 ) configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the high-side MOS transistor. The booster circuit has power supply capability which varies depending on the load control signal.

First claim

The invention claimed is:

1. A power supply circuit comprising:
a transistor configured to turn on and off a voltage supplied to a load;
a booster circuit configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the transistor; and
a power supply capability switching circuit configured to switch power supply capability of the booster circuit depending on the number of pulses per unit time of a load control signal that controls on and off of the transistor,
wherein the power supply capability switching circuit includes a drive pattern decoder that determines a drive pattern for the load control signal, and the booster circuit is controlled based on the drive pattern without directly specifying an operation mode of the boost circuit.

2. The power supply circuit according to claim 1 , wherein the power supply capability switching circuit is configured to switch the power supply capability so as to set the power supply capability to be lower when the load control signal indicates that an amount of power supplied to the load is smaller.

3. The power supply circuit according to claim 2 , wherein the power supply capability switching circuit is configured to output a power-supply-capability-switching clock signal having a frequency corresponding to the load control signal, and
wherein the frequency of the power-supply-capability-switching clock signal is lower when the load control signal indicates that the amount of power supplied to the load is smaller.

4. The power supply circuit according to claim 2 , wherein the power supply capability switching circuit is configured to output a first clock signal of which the frequency is a first frequency as the power-supply-capability-switching clock signal when the load control signal indicates that the amount of power supplied to the load is equal to or more than a threshold value, and to output a second clock signal of which the frequency is a second frequency lower than the first frequency as the power-supply-capability-switching clock signal when the load control signal indicates that the amount of power supplied to the load is less than the threshold value.

5. The power supply circuit according to claim 4 , wherein the power supply capability switching circuit includes:
an oscillation circuit configured to generate a third clock signal; and
a frequency converter circuit configured to convert the frequency of the third clock signal into the first frequency and the second frequency to generate the first clock signal and the second clock signal,
wherein the frequency converter circuit is configured to generate the first clock signal when the load control signal indicates that the amount of power supplied is equal to or more than the threshold value, and to generate the second clock signal when the load control signal indicates that the amount of power supplied is less than the threshold value.

6. The power supply circuit according to claim 4 , wherein the power supply capability switching circuit includes:
a first oscillation circuit configured to generate the first clock signal;
a second oscillation circuit configured to generate the second clock signal; and
a selection circuit configured to select the first oscillation circuit to output the first clock signal when the load control signal indicates that the amount of power supplied is equal to or more than the threshold value, and to select the second oscillation circuit to output the second clock signal when the load control signal indicates that the amount of power supplied is less than the threshold value.

7. The power supply circuit according to claim 4 , wherein the threshold value is zero.

8. The power supply circuit according to claim 3 , wherein the power supply capability switching circuit includes:
an oscillation circuit configured to generate a third clock signal;
a divider configured to perform frequency-dividing the third clock signal at different dividing ratios to generate a plurality of clock signals having different frequencies; and
a selection unit configured to select the clock signal having the frequency corresponding to the load control signal out of the plurality of clock signals generated by the divider as the power-supply-capability-switching clock signal,
wherein the selection unit is configured to select the clock signal having a lower frequency when the load control signal indicates that the amount of power supplied to the load is smaller.

9. The power supply circuit according to claim 3 , wherein the power supply capability switching circuit includes:
an oscillation circuit configured to generate a third clock signal; and
a divider configured to perform frequency-dividing the third clock signal to generate the power-supply-capability-switching clock signal,
wherein the divider is configured to switch the dividing ratio to a dividing ratio for lowering the frequency when the load control signal indicates that the amount of power supplied to the load is smaller.

10. The power supply circuit according to claim 3 , wherein the booster circuit is a charge pump circuit configured to boost the voltage of the input power depending on the power-supply-capability-switching clock signal.

11. The power supply circuit according to claim 1 , further comprising a load driving circuit that drives the load by controlling the transistor on the basis of the load control signal.

12. The power supply circuit according to claim 11 , wherein the transistor is inside the load driving circuit.

13. The power supply circuit according to claim 1 , wherein the transistor is connected in series to at least one additional transistor.

14. The power supply circuit according to claim 1 , wherein the load is a motor connected to an output terminal.

15. The power supply circuit according to claim 1 , wherein the load control signal is inputted by a control input terminal.

16. A power supply circuit comprising:
a transistor configured to turn on and off a voltage supplied to a load;
a booster circuit configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the transistor; and
a power supply capability switching circuit configured to switch power supply capability of the booster circuit depending on a result of comparing a threshold value and a pulse width of a load control signal that controls on and off of the transistor,
wherein the power supply capability switching circuit includes a drive pattern decoder that determines a drive pattern for the load control signal, and the booster circuit is controlled based on the drive pattern without directly specifying an operation mode of the boost circuit.

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Aiura Masami

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title