Pressure sensor assembly for use in implantable medical device including a substrate having via that extends through substrate along via axis between first major surface and second major surface of substrate

Patent metadata

Field	Value
Publication number	US-11725995-B2
Application number	US-202217571825-A
Country	US
Kind code	B2
Filing date	Jan 10, 2022
Priority date	Feb 1, 2021
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Various embodiments of a pressure sensor assembly and an implantable medical device that includes such assembly are disclosed. The assembly includes a substrate having a via that extends through the substrate along a via axis between a first major surface and a second major surface of the substrate, a membrane disposed on the first major surface of the substrate and over the via, and a patterned metal layer disposed on a first major surface of the membrane, a portion of such layer including a first capacitor plate. The assembly further includes an integrated circuit disposed adjacent to the first major surface of the membrane and electrically connected to the metal layer. The integrated circuit includes a second capacitor plate disposed on or within a substrate of the integrated circuit. The first capacitor plate and the second capacitor plate form a variable capacitor disposed along the via axis.

First claim

What is claimed is:

1. A pressure sensor assembly comprising:
a substrate comprising a via that extends through the substrate along a via axis between a first major surface and a second major surface of the substrate, wherein the via axis is substantially orthogonal to the first major surface of the substrate;
a membrane comprising a first major surface and a second major surface, wherein the second major surface of the membrane is disposed on the first major surface of the substrate and over the via;
a patterned metal layer disposed on the first major surface of the membrane, wherein a portion of the metal layer aligned with the via along the via axis comprises a first capacitor plate; and
an integrated circuit disposed adjacent to the first major surface of the membrane and over the via, wherein the integrated circuit is electrically connected to the metal layer disposed on the first major surface of the membrane, wherein the integrated circuit comprises an integrated circuit substrate comprising a first major surface and a second major surface, and a second capacitor plate disposed on or within the substrate, wherein the second capacitor plate is substantially parallel to and spaced apart from the first capacitor plate disposed on the membrane;
wherein the first capacitor plate and the second capacitor plate form a variable capacitor disposed along the via axis.

2. The assembly of claim 1 , wherein the second capacitor plate is disposed on the second major surface of the integrated circuit substrate that faces the first major surface of the membrane.

3. The assembly of claim 1 , wherein the integrated circuit further comprises a reference capacitor comprising a first reference capacitor plate, a second reference capacitor plate, and a dielectric layer disposed between the first reference capacitor plate and the second reference capacitor plate.

4. The assembly of claim 3 , wherein the second reference capacitor plate comprises the second capacitor plate of the variable capacitor.

5. The assembly of claim 3 , wherein the dielectric layer of the reference capacitor is formed by a portion of a passivation layer that is disposed on the second major surface of the integrated circuit substrate.

6. The assembly of claim 1 , further comprising a seal ring disposed between the integrated circuit and the membrane, wherein the seal ring forms a hermetic enclosure between the membrane and the integrated circuit.

7. The assembly of claim 1 , further comprising a nonconductive layer disposed on the second major surface of the substrate, wherein the via is disposed through the nonconductive layer and the substrate.

8. The assembly of claim 1 , further comprising one or more interconnect pads disposed adjacent to the first major surface of the integrated circuit substrate.

9. The assembly of claim 1 , wherein the membrane is bonded to the first major surface of the substrate.

10. An implantable medical device comprising:
a housing; and
a pressure sensor assembly comprising:
a substrate comprising a via that extends through the substrate along a via axis between a first major surface and a second major surface of the substrate, wherein the via axis is substantially orthogonal to the first major surface of the substrate;
a membrane comprising a first major surface and a second major surface, wherein the second major surface of the membrane is disposed on the first major surface of the substrate and over the via;
a patterned metal layer disposed on the first major surface of the membrane, wherein a portion of the metal layer aligned with the via along the via axis comprises a first capacitor plate; and
an integrated circuit disposed adjacent to the first major surface of the membrane and over the via, wherein the integrated circuit is electrically connected to the metal layer disposed on the first major surface of the membrane, wherein the integrated circuit comprises an integrated circuit substrate comprising a first major surface and a second major surface, and a second capacitor plate disposed on or within the substrate, wherein the second capacitor plate is substantially parallel to and spaced apart from the first capacitor plate disposed on the membrane;
wherein the first capacitor plate and the second capacitor plate form a variable capacitor disposed along the via axis.

11. The device of claim 10 , further comprising a power source disposed within the housing and electrically connected to the pressure sensor assembly.

12. The device of claim 10 , wherein the integrated circuit of the pressure sensor assembly further comprises a reference capacitor comprising a first reference capacitor plate, a second reference capacitor plate, and a dielectric layer disposed between the first reference capacitor plate and the second reference capacitor plate.

13. The device of claim 12 , wherein the second reference capacitor plate comprises the second capacitor plate of the variable capacitor.

14. The device of claim 12 , wherein the dielectric layer of the reference capacitor is formed by a portion of a passivation layer that is disposed on the second major surface of the integrated circuit substrate.

15. The device of claim 12 , further comprising a controller electrically connected to the pressure sensor assembly, wherein the controller is adapted to:
detect a first capacitance of the variable capacitor of the pressure sensor assembly;
detect a second capacitance of the reference capacitor of the pressure sensor assembly; and
compare the first capacitance and the second capacitance.

16. A method comprising:
disposing a membrane adjacent to a first major surface of a substrate;
disposing a via through the substrate such that it extends along a via axis between the first major surface and a second major surface of the substrate, wherein the membrane is disposed over the via, and further wherein the via axis is substantially orthogonal to the first major surface of the substrate;
disposing a metal layer on the membrane such that the membrane is disposed between the metal layer and the substrate;
patterning the metal layer such that a portion of the metal layer forms a first capacitor plate that is aligned with the via along the via axis; and
disposing an integrated circuit adjacent to the membrane and over the via, wherein the integrated circuit is electrically connected to the metal layer, and further wherein the integrated circuit comprises an integrated circuit substrate comprising a first major surface and a second major surface, and a second capacitor plate disposed on or within the substrate, wherein the second capacitor plate is substantially parallel to and spaced apart from the first capacitor plate disposed on the membrane;
wherein the first capacitor plate and the second capacitor plate form a variable capacitor disposed along the via axis.

17. The method of claim 16 , further comprising disposing a nonconductive layer on the second major surface of the substrate.

18. The method of claim 17 , wherein the nonconductive layer is disposed on the second major surface of the substrate prior to disposing the via through the substrate such that the via extends through the nonconductive layer and the substrate.

19. The method of claim 16 , wherein disposing the membrane comprises bonding the membrane to the first major surface of the substrate.

20. The method of claim 19 , wherein bonding the membrane comprises high temperature fusion bonding the membrane to the first major surface of the substrate.

Assignees

• Medtronic Inc

Inventors

• Fenner Andreas
• Ruben David A
• Ries Andrew J
• Patel Chetan

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• G01L9/0073 Primary

  using a semiconductive diaphragm · CPC title

• B23K26/20

  Bonding (soldering by means of radiant energy B23K1/005) · CPC title