Integrated circuit read only memory (ROM) structure

Patent metadata

Field	Value
Publication number	US-11723194-B2
Application number	US-202117193594-A
Country	US
Kind code	B2
Filing date	Mar 5, 2021
Priority date	Mar 5, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.

First claim

What is claimed is:

1. An integrated circuit read-only memory (ROM) structure, comprising:
a first transistor comprising a first gate electrode, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
a second transistor comprising a second gate electrode, a second drain, the first source, and a second drain conductive line over the second drain;
a bit line electrically connecting the first drain conductive line to the second drain conductive line; and
a first trench isolation structure between the first source and the second drain and which electrically isolates the first source from the second drain,
wherein the first drain and the second drain are separated by two conductive line separation intervals.

2. The integrated circuit ROM structure of claim 1 , wherein the first gate electrode and the second gate electrode are separated by one gate electrode separation interval.

3. The integrated circuit ROM structure of claim 1 , further comprising a power rail, wherein the first source conductive line and a second source conductive line are electrically connected to the power rail.

4. The integrated circuit ROM structure of claim 1 , further comprising a third gate electrode, a second source, a source conductive line electrically connecting the first source conductive line to a second source conductive line, and a third drain with a third drain conductive line, wherein the third gate electrode is between the third drain and the second source.

5. The integrated circuit ROM structure of claim 4 , further comprising a third transistor with the third drain, the third gate electrode, and the second drain, wherein the second drain of the second transistor is configured to provide a bit value for the third transistor.

6. An integrated circuit read-only memory (ROM) structure, comprising:
a first transistor comprising:
a first gate electrode,
a first gate electrode contact electrically connected to the first gate electrode,
a first source,
a first source conductive line electrically connected to the first source,
a first source contact electrically connected to the first source conductive line, and
a first drain; and

a power rail electrically connected to the first source contact and a first gate electrode tie-off contact, wherein the first gate electrode tie-off contact electrically connects the power rail to the first gate electrode;
a second transistor comprising:
a second gate electrode,
a second gate electrode contact electrically connected to the second gate electrode,
a second source,
a second source conductive line electrically connected to the second source,
a second source contact electrically connected to the second source conductive line and the power rail, and
the first drain; and

a third transistor comprising:
a third gate electrode,
the first source, and
a second drain,

wherein the third gate electrode is separated from the first gate electrode by one gate electrode separation interval, and the second gate electrode is separated from the third gate electrode by two gate electrode separation intervals.

7. The integrated circuit ROM structure of claim 6 , further comprising a second gate electrode tie-off contact electrically connected to the second gate electrode and the power rail.

8. The integrated circuit ROM structure of claim 6 , wherein the first source conductive line is separated from the second source conductive line by two conductive line intervals.

9. The integrated circuit ROM structure of claim 6 , further comprising:
a first drain conductive line electrically connected to the first drain;
a second drain conductive line electrically connected to the second drain;
a bit line;
a first drain contact electrically connecting the bit line to the first drain conductive line; and
a second drain contact electrically connecting the bit line to the second drain conductive line.

10. The integrated circuit ROM structure of claim 9 , further comprising a third gate electrode contact electrically connected to the third gate electrode.

11. An integrated circuit read-only memory (ROM) structure, comprising:
a first drain contact;
a drain conductive line electrically connected to the first drain contact;
a first transistor comprising:
a first gate electrode,
a first gate electrode contact,
a first source,
a first source conductive line electrically connected to the first source,
a first source contact electrically connected to the first source conductive line,
a first drain electrically connected to the drain conductive line, and
a power rail electrically connected to the first source contact; and

a second transistor comprising:
a second gate electrode, the second gate electrode comprising a first portion and a second portion, the first portion and the second portion being separated by an isolation structure,
a second gate electrode contact connected to the isolation structure,
a second source,
a second source conductive line connected to the second source,
a second source contact connected to the second source conductive line and the power rail, and
a second drain electrically connected to the drain conductive line.

12. An integrated circuit ROM structure according to claim 11 , wherein:
the isolation structure extends across an active area.

13. An integrated circuit ROM structure according to claim 12 , wherein:
the first portion of the second gate electrode is on a first side of the active area; and
the second portion of the second gate electrode is on a second side of the active area opposite the first side.

14. An integrated circuit ROM structure according to claim 12 , further comprising:
a bit line;
a first word line; and
a second word line, wherein the bit line, first word line, and second word line are parallel to the power rail.

15. An integrated circuit ROM structure according to claim 14 , wherein:
the bit line is electrically connected to the first drain contact;
the first word line is electrically connected to the first gate electrode contact; and
the second word line is electrically connected to the second gate electrode contact.

16. An integrated circuit ROM structure according to claim 15 , wherein:
the first word line comprises a first word line first portion and a first word line second portion, wherein the first word line second portion is electrically connected to the first gate electrode contact; and
the second word line comprises a second word line first portion and a second word line second portion, wherein the second word line first portion is electrically connected to the second gate electrode contact.

17. An integrated circuit ROM structure according to claim 14 , further comprising:
a third transistor comprising:
a third gate electrode, the third gate electrode comprising a first portion and a second portion, the first portion of the third gate electrode and the second portion of the third gate electrode being separated by a further isolation structure,
a third gate electrode contact connected to the further isolation structure,
a third source,
a third source conductive line connected to the third source,
a third source contact connected to the third source conductive line and the power rail, and
a third drain electrically connected to the drain conductive line.

18. An integrated circuit ROM structure according to claim 17 , wherein:
the bit line is electrically connected to the first drain contact;
the first word line is electrica

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Geng-Cing
• Lu Ze-Sian
• Chang Meng-Sheng
• Huang Chia-En
• Yang Jung-Ping
• Chen Yen-Huei

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title