Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11721597-B2
Application number	US-202117461479-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 30, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A semiconductor device and a method for detecting a defect in a semiconductor device are provided. The semiconductor device includes a packaging structure. The packaging structure includes a redistribution layer and a detecting component disposed in the redistribution layer. The semiconductor device further includes a cooling plate over the packaging structure and a fixing component penetrating through the packaging structure and the cooling plate. The packaging structure and the cooling plate are fixed by the fixing component. The detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a packaging structure comprising a redistribution layer and a detecting component disposed in the redistribution layer;
a cooling plate over the packaging structure; and
a fixing component penetrating through the packaging structure and the cooling plate, the packaging structure and the cooling plate being fixed by the fixing component,
wherein the detecting component is in a chain configuration having a ring shaped structure circling around the fixing component.

2. The semiconductor device of claim 1 , wherein the redistribution layer comprises a plurality of first conductive layers in stack and a plurality of first conductive vias coupling the first conductive layers.

3. The semiconductor device of claim 2 , wherein the detecting component comprises a plurality of second conductive layers in stack around the fixing component, and a plurality of second conductive vias coupling the second conductive layers.

4. The semiconductor device of claim 3 , wherein the second conductive layers and the second conductive vias are isolated from the first conductive layers and the first conductive vias.

5. The semiconductor device of claim 3 , wherein the plurality of second conductive layers have the same diameter around the fixing component.

6. The semiconductor device of claim 1 , wherein the detecting component comprises a first chain structure and a second chain structure, and wherein the first chain structure has the ring shaped structure circling around the fixing component and the second chain structure is disposed at the periphery of the ring shaped structure.

7. The semiconductor device of claim 1 , further comprising a first probe pad and a second probe pad electrically connected to two ends of the detecting component, and wherein the first probe pad and the second probe pad are disposed at an upper surface of the packaging structure.

8. The semiconductor device of claim 7 , wherein the first probe pad and the second probe pad are exposed from the cooling plate.

9. The semiconductor device of claim 1 , further comprising a seal ring disposed between the fixing component and the detecting component.

10. The semiconductor device of claim 9 , wherein the seal ring is electrically isolated from the detecting component.

11. A semiconductor device, comprising:
a packaging structure comprising a die, a molding adjacent to the die, and a detecting component over the die and the molding;
a cooling plate over the packaging structure; and
a fixing component penetrating through the molding of the packaging structure and the cooling plate, the packaging structure and the cooling plate being fixed by the fixing component,
wherein the detecting component is disposed around and vertically along the fixing component and electrically isolated from the die of the packaging structure.

12. The semiconductor device of claim 11 , wherein the packaging structure further comprises a redistribution layer over the die and the molding and the detecting component is disposed in the redistribution layer.

13. The semiconductor device of claim 12 , wherein the redistribution layer comprises a plurality of first conductive layers in stack and a plurality of first conductive vias coupling the first conductive layers, and the detecting component is electrically isolated from the first conductive layers and the first conductive vias.

14. The semiconductor device of claim 13 , wherein the first conductive layers and the first conductive vias are electrically connected to the die.

15. The semiconductor device of claim 11 , wherein the packaging structure further comprises a bump over the die, and wherein one end of the detecting component is electrically connected to the bump.

16. The semiconductor device of claim 15 , wherein the cooling plate comprises an opening through the cooling plate, and wherein the opening exposes the bump.

17. The semiconductor device of claim 11 , wherein the packaging structure further comprises a seal ring between the fixing component and the detecting component, and wherein the seal ring contacts the die.

18. A method for detecting a defect in a semiconductor device, comprising:
forming a hole through a packaging structure comprising a redistribution layer and a detecting component disposed in the redistribution layer, wherein the detecting component is located around and vertically along a hole;
fixing a cooling plate to the packaging structure by a fixing component, wherein the fixing component penetrates through the hole of the packaging structure and the cooling plate;
probing the detecting component to determine an electrical connection status of the detecting component; and
recognizing a defect when the connection status of the detecting component indicates an open circuit.

19. The method of claim 18 , wherein the semiconductor device further comprises a first probe pad and a second probe pad electrically connected to two ends of the detecting component, and the connection status of the detecting component is determined by providing a test signal to the first probe pad and detecting the test signal at the second probe pad.

20. The method of claim 19 , wherein the first probe pad, the detecting component and the second probe pad are configured to transmit the test signal from the first probe pad to an uppermost conductive layer of the detecting device, from the uppermost conductive layer to a lowermost conductive layer of the detecting component, and from the lowermost conductive layer of the detecting component to the second probe pad.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yang-Che
• Lin Chen-Hua
• Liang Victor Chiang
• Tseng Huang-Wen
• Liu Chwen-Ming

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title