Method for forming contact structures in three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-11716843-B2
Application number	US-202017015213-A
Country	US
Kind code	B2
Filing date	Sep 9, 2020
Priority date	Mar 19, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes forming multiple openings in staircase regions, periphery device regions, and substrate contact regions of a 3D NAND memory device. The openings can be formed by a photolithography process followed by multiple etching processes. The openings can include complete openings that expose the underlying layer and mid-way openings where a remaining portion of the photoresist still exists between the opening and the underlying layer. The remaining portion of the photoresist can delay the etching process in the shorter openings for the upper level staircase structure during the formation of the deeper openings for the lower level staircase structure. Conductive material is deposited into the openings to form contact structures for structures such as substrate contact pads, upper and lower level staircase structures, and/or peripheral devices.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory structure, comprising:
forming a dielectric layer on a substrate;
forming upper level and lower level staircase structures in the dielectric layer;
disposing a first etch stop layer (ESL) on the dielectric layer;
disposing a hard mask layer on the first ESL;
disposing a second ESL on the hard mask layer;
performing a first etching process to form a first plurality of openings in the second ESL, wherein the first plurality of openings are formed above the lower level staircase structure;
performing a second etching process, comprising:
extending the first plurality of openings into the hard mask layer; and
forming a second plurality of openings in the second ESL, wherein the second plurality of openings are formed above the upper and lower level staircase structures; and
performing additional sequential etching processes, comprising:
exposing the hard mask layer, the first ESL, and the dielectric layer in the first plurality of openings and in the second plurality of openings.

2. The method of claim 1 , wherein performing the additional etching processes comprises:
performing a third etching process, comprising:
extending the first plurality of openings into the dielectric layer until a topmost conductive layer of the lower level staircase structure is exposed in an opening of the first plurality of openings; and
extending the second plurality of openings into the hard mask layer;
performing a fourth etching process to etch a portion of the hard mask layer until the first ESL is exposed in the second plurality of openings; and
performing a fifth etching process, comprising:
extending the first plurality of openings such that each opening of the first plurality of openings is in physical contact with a corresponding conductive layer of the lower level staircase structure; and
extending the second plurality of openings such that each opening of the second plurality of openings is in physical contact with a corresponding conductive layer of the upper level staircase structure.

3. The method of claim 2 , wherein performing the third etching process comprises extending the first plurality of openings through the first ESL.

4. The method of claim 2 , wherein performing the fourth etching process comprises etching through the hard mask layer in the second plurality of openings.

5. The method of claim 1 , further comprising disposing conductive material in the first and second pluralities of openings to form word line contacts for the lower and upper level staircase structures.

6. The method of claim 5 , further comprising performing a planarization process on the second ESL and the disposed conductive material.

7. The method of claim 1 , further comprising forming a photoresist layer on the second ESL and exposing the photoresist layer under a reticle.

8. The method of claim 7 , wherein the reticle comprises transparent regions, semi-transparent regions, and opaque regions.

9. The method of claim 8 , further comprising:
forming a first plurality of photoresist openings under the transparent regions of the reticle, wherein the first plurality of photoresist openings have a first depth that is about equal to a thickness of the photoresist layer; and
forming a second plurality of photoresist openings under the semi-transparent regions, wherein the second plurality of photoresist openings have a second depth that is less than the thickness of the photoresist layer.

10. The method of claim 9 , wherein performing the first etching process comprises removing portions of the second ESL through the first plurality of photoresist openings.

11. The method of claim 9 , further comprising extending the second plurality of photoresist openings to expose portions of the second ESL, and wherein performing the second etching process comprises removing the exposed portions of the second ESL.

12. A method for forming a three-dimensional (3D) memory structure, comprising:
forming a dielectric layer on a substrate;
forming upper level and lower level staircase structures in the dielectric layer;
disposing a photoresist layer on the dielectric layer;
exposing the photoresist layer under a reticle, wherein the reticle comprises transparent regions over the lower level staircase structures, semi-transparent regions over the upper level staircase structures, and opaque regions;
forming a first plurality of openings in the photoresist layer under the transparent regions, wherein the first plurality of openings have a depth that is about equal to a thickness of the photoresist layer;
forming a second plurality of openings in the photoresist layer under the semi-transparent regions, wherein the second plurality of openings have a depth that is less than the thickness of the photoresist layer;
performing one or more etching processes, comprising:
exposing the dielectric layer in the first plurality of openings and in the second plurality of openings; and
disposing conductive material in the first and second pluralities of openings and on conductive layers of the lower and upper level staircase structures, respectively.

13. The method of claim 12 , further comprising:
extending the first plurality of openings and exposing conductive layers of the lower level staircase structures in the first plurality of openings; and
extending the second plurality of openings and exposing conductive layers of the upper level staircase structures in the second plurality of openings.

14. The method of claim 12 , further comprising forming a contact pad in the substrate and performing the one or more etching processes comprises exposing the contact pad through at least one opening of the first plurality of openings.

15. The method of claim 12 , further comprising forming terminals of a semiconductor device in the substrate and performing the one or more etching processes comprises exposing the terminals through at least one opening of the first plurality of openings.

16. The method of claim 12 , further comprising disposing an etch stop layer over the dielectric layer, and the one or more etching processes comprise a first etching process to remove a portion of the etch stop layer through the first plurality of openings and to extend the second plurality of openings through the photoresist layer.

17. The method of claim 16 , further comprising disposing a hard mask layer over the dielectric layer, and the one or more etching processes comprise a second etching process to extend the first plurality of openings through the hard mask layer and to remove a portion of the etch stop layer through the second plurality of openings.

18. A method for forming a three-dimensional (3D) memory structure, comprising:
forming a dielectric layer on a substrate;
forming a contact pad in the substrate;
forming staircase structures in the dielectric layer;
disposing a photoresist layer on the dielectric layer;
exposing the photoresist layer under a reticle, wherein the reticle comprises transparent regions over the contact pad and semi-transparent regions over the staircase structures;
forming a first plurality of openings in the photoresist layer under the transparent regions, wherein the first plurality of openings have a depth that is about equal to a thickness of the photoresist layer;
forming a second plurality of openings in the photoresist layer under the semi-transparent regions, wherein the second plurality of openings have a depth that is less than the thickness of the photoresist layer;
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Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Yang Han
• Zeng Fanqing
• Zhang Fushan
• Xu Qianbing
• Wang Enbo

Classifications

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B69/00 Primary

  Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices · CPC title