Three-dimensional semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10818678-B2
Application number	US-201815954151-A
Country	US
Kind code	B2
Filing date	Apr 16, 2018
Priority date	Jul 31, 2017
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate comprising a peripheral circuit region, a cell array region, and a connection region disposed between the peripheral circuit region and the cell array region;
a plurality of peripheral gate stacks disposed in the peripheral circuit region of the substrate; and
an electrode structure disposed in the cell array region of the substrate, wherein the electrode structure comprises a lower electrode, a lower insulating layer disposed on the lower electrode, and a plurality of upper electrodes and a plurality of upper insulating layers alternately stacked on the lower insulating layer,
wherein the lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks,
wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer, and the first lower insulating layer is disposed between the second lower insulating layer and the substrate,
wherein the second lower insulating layer has different thicknesses in the connection region,
wherein the first lower insulating layer comprises a first insulating material, and the second lower insulating layer comprises a second insulating material different from the first insulating material.

2. The three-dimensional semiconductor memory device of claim 1 , wherein a thickness of the second lower insulating layer is less than a thickness of the first lower insulating layer.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the second lower insulating layer comprises:
a first portion disposed in the cell array region; and
a second portion disposed in the peripheral circuit region,
wherein a thickness of the second portion is less than a thickness of the first portion.

4. The three-dimensional semiconductor memory device of claim 1 , wherein a sidewall of the second lower insulating layer is substantially aligned with a sidewall of a lowermost one of the upper electrodes.

5. The three-dimensional semiconductor memory device of claim 1 , wherein the upper insulating layers comprise the second insulating material.

6. The three-dimensional semiconductor memory device of claim 1 , wherein a thickness of the first lower insulating layer is thinner in the cell array region than in the peripheral circuit region.

7. The three-dimensional semiconductor memory device of claim 1 , wherein bottom surfaces of the peripheral gate stacks are positioned below a bottom surface of the lower electrode.

8. The three-dimensional semiconductor memory device of claim 1 , wherein top surfaces of the peripheral gate stacks are positioned between a top surface of the lower electrode and a bottom surface of a lowermost one of the upper electrodes.

9. The three-dimensional semiconductor memory device of claim 1 , wherein the first lower insulating layer comprises a portion disposed between adjacent ones of the peripheral gate stacks.

10. The three-dimensional semiconductor memory device of claim 1 , wherein the first lower insulating layer defines an air gap disposed between adjacent ones of the peripheral gate stacks.

11. The three-dimensional semiconductor memory device of claim 1 , further comprising:
a plurality of vertical structures, wherein the vertical structures penetrate the electrode structure in the cell array region and are connected to the substrate.

12. A three-dimensional semiconductor memory device, comprising:
a substrate comprising a peripheral circuit region and a cell array region;
a plurality of peripheral gate stacks disposed in the peripheral circuit region of the substrate; and
an electrode structure disposed in the cell array region of the substrate, wherein the electrode structure comprises a lower electrode, a lower insulating layer disposed on the lower electrode, and a plurality of upper electrodes and a plurality of upper insulating layers alternately stacked on the lower insulating layer,
wherein the lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks,
wherein a top surface of the lower insulating layer is lower in the cell array region than in the peripheral circuit region,
wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer, and the first and second lower insulating layers are sequentially stacked,
wherein a top surface of the first lower insulating layer is lower in the cell array region than in the peripheral circuit region, and
wherein a top surface of the second lower insulating layer is lower in the cell array region than in the peripheral circuit region.

13. The three-dimensional semiconductor memory device of claim 12 ,
wherein the first lower insulating layer comprises a first insulating material, and the second lower insulating layer comprises a second insulating material different from the first insulating material.

14. The three-dimensional semiconductor memory device of claim 13 , wherein a first thickness of the first lower insulating layer in the cell array region is less than a second thickness of the first lower insulating layer in the peripheral circuit region.

15. The three-dimensional semiconductor memory device of claim 13 , wherein the upper insulating layers comprise the second insulating material.

16. The three-dimensional semiconductor memory device of claim 13 , further comprising:
a dummy sacrificial pattern disposed in the peripheral circuit region and conformally covering the peripheral gate stacks,
wherein the dummy sacrificial pattern comprises a third insulating material different from the first and second insulating materials.

17. The three-dimensional semiconductor memory device of claim 16 , wherein the first lower insulating layer comprises a portion disposed between the peripheral gate stacks and on the dummy sacrificial pattern, and
the second lower insulating layer extends from ft the top surface of the first lower insulating layer to a top surface of a portion of the dummy sacrificial pattern.

18. A three-dimensional semiconductor memory device, comprising:
a substrate comprising a peripheral circuit region and a cell array region;
a plurality of peripheral gate stacks disposed in the peripheral circuit region of the substrate;
an electrode structure disposed in the cell array region of the substrate, wherein the electrode structure comprises a lower electrode, a lower insulating layer disposed on the lower electrode, and a plurality of upper electrodes and a plurality of upper insulating layers alternately stacked on the lower insulating layer; and
a dummy sacrificial pattern disposed in the peripheral circuit region and conformally covering the peripheral gate stacks,
wherein the lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks,
wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer, and the first and second lower insulating layers are sequentially stacked,
wherein the first lower insulating layer comprises a portion disposed between the peripheral gate stacks and on the dummy sacrificial pattern,
wherein the second lower insulating layer extends from a top surface of the first lower insulating layer to a top surface of a portion of the dummy sacrificial pattern, and
wherein the first lower insulating layer is located at a level that is substantia

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Lee Dong-Sik
• Lim Joon-Sung

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10B41/41 Primary

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/30

  characterised by the memory core region · CPC title