Asynchronous circuit with threshold logic

Patent metadata

Field	Value
Publication number	US-11716083-B1
Application number	US-202117645840-A
Country	US
Kind code	B1
Filing date	Dec 23, 2021
Priority date	Dec 23, 2021
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

First claim

We claim:

1. An apparatus comprising:
a first threshold gate to receive a first set of inputs and to generate a first output in accordance with a first threshold of the first threshold gate and in accordance with logic values of the first set of inputs;
a first transistor having a first gate terminal coupled to the first output;
a second threshold gate to receive a second set of inputs and to generate a second output in accordance with a second threshold of the second threshold gate and in accordance with logic values of the second set of inputs;
a second transistor having a second gate terminal coupled to the second output, wherein the first transistor and the second transistor are coupled in series, wherein the first gate terminal and the second gate terminal are not common gate terminals, wherein the first threshold gate includes:
a third transistor which is controllable by a first control; and
a fourth transistor which is controllable by a second control which is separate from the first control, wherein the third transistor and the fourth transistor are to reset or preset the first output in accordance with the first control and the second control.

2. The apparatus of claim 1 , wherein the first threshold gate, the first transistor, the second threshold gate, and the second transistor are part of an asynchronous circuit.

3. The apparatus of claim 1 , wherein the first transistor is a p-type transistor, and wherein the second transistor is an n-type transistor.

4. The apparatus of claim 1 comprises a memory circuitry coupled to the first transistor and the second transistor.

5. The apparatus of claim 4 , wherein the memory circuitry includes a first inversion circuitry and a second inversion circuitry, and wherein the first inversion circuitry is coupled to the second inversion circuitry in a ring configuration.

6. The apparatus of claim 1 , wherein the first threshold gate comprises:
a first capacitor having a first terminal coupled to receive a first input of the first set of inputs, the first capacitor having a second terminal coupled to a first summing node; and
a second capacitor having a third terminal coupled to receive a second input of the first set of inputs, the second capacitor having a fourth terminal coupled to the first summing node.

7. The apparatus of claim 6 , wherein the first summing node is coupled to the first gate terminal of the first transistor.

8. The apparatus of claim 6 , wherein the first capacitor and the second capacitor have linear dielectric.

9. The apparatus of claim 1 , wherein the second threshold gate comprises:
a first capacitor having a first terminal coupled to receive a first input of the second set of inputs, the first capacitor having a second terminal coupled to a second summing node; and
a second capacitor having a third terminal coupled to receive a second input of the second set of inputs, the second capacitor having a fourth terminal coupled to the second summing node.

10. The apparatus of claim 9 , wherein the second summing node is coupled to the second gate terminal of the second transistor.

11. The apparatus of claim 9 , wherein the first capacitor and the second capacitor have linear dielectric.

12. The apparatus of claim 9 , wherein the first capacitor and the second capacitor have non-linear polar dielectric.

13. The apparatus of claim 12 , wherein the non-linear polar dielectric includes a ferroelectric material or a paraelectric material.

14. The apparatus of claim 13 , wherein the ferroelectric material includes one or more of:
Bismuth ferrite (BFO) with a first doping material, wherein the first doping material is one of Lanthanum or elements from lanthanide series of a periodic table;
Lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);
a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
Hafnium oxides as Hf1−x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where ‘y’ includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;
Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

15. The apparatus of claim 13 , wherein the paraelectric material includes one or more of: SrTiO3, Ba(x)Sr(y)TiO3, HfZrO2, Hf—Si—O, BaTiO3, La-substituted PbTiO3, lead zirconate titanate, or PMN-PT (lead magnesium niobate-lead titanate) based relaxor ferroelectrics.

16. An apparatus comprising:
a first transistor of a first conductivity type;
a second transistor of a second conductivity type, wherein the second transistor is coupled in series with the first transistor, wherein the first conductivity type is different from the second conductivity type;
a first threshold gate comprising a first capacitive input circuit, wherein the first threshold gate is to drive the first transistor;
a second threshold gate comprising a second capacitive input circuit, wherein the second threshold gate is to drive the second transistor, wherein the first transistor has a first gate terminal, wherein the second transistor has a second gate terminal, and wherein the first gate terminal and the second gate terminal are not common gate terminals, wherein the first threshold gate includes:
a third transistor which is controllable by a first control; and
a fourth transistor which is controllable by a second control which is separate from the first control, wherein the third transistor and the fourth transistor are to reset or preset an output of the first threshold gate in accordance with the first control and the second control.

17. The apparatus of claim 16 , wherein the first threshold gate and the second threshold gate have adjustable thresholds.

18. The apparatus of claim 16 , wherein the first capacitive input circuit includes capacitors which comprises one of: linear dielectric, paraelectric dielectric, or ferroelectric dielectric.

19. A system comprising:
a memory circuitry to store one or more instructions;
a processor circuitry coupled to the memory circuitry; and
a communication interface coupled to the processor circuitry, wherein the processor circuitry is to execute the one or more instructions, wherein the processor circuitry includes an asynchronous circuitry, wherein the asynchronous circuitry includes:
a first transistor of a first conductivity type;
a second transistor of a second conductivity type, wherein the

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Imam Nabil
• Odinaka Ikenna
• Rios Rafael
• Dokania Rajeev Kumar
• Mathuriya Amrita

Classifications

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H03K19/0027 Primary

  in field effect transistor circuits · CPC title

• H01L28/55

  Electricity · mapped topic

• H01L28/65

  Electricity · mapped topic