Nonvolatile memory device and nonvolatile memory system including the same

Patent metadata

Field	Value
Publication number	US-11715713-B2
Application number	US-202117405637-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Oct 8, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a substrate including a first surface and a second surface opposite to the first surface in a first direction;
a common source line on the first surface of the substrate;
a plurality of word lines stacked on the common source line;
a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate;
an insulating layer on the second surface of the substrate;
a first contact plug penetrating the first insulating pattern and extending in the first direction;
a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug;
an upper bonding metal connected to the first contact plug and connected to a circuit element; and
a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

2. The nonvolatile memory device of claim 1 , wherein a sidewall of the first insulating pattern is surrounded by the substrate, and
the first insulating pattern is exposed on the first surface of the substrate and the second surface of the substrate.

3. The nonvolatile memory device of claim 2 , wherein the first contact plug is in contact with the second contact plug on the second surface.

4. The nonvolatile memory device of claim 1 , wherein a width of the first insulating pattern in the second direction is greater than a width of the first contact plug in the second direction.

5. The nonvolatile memory device of claim 4 , wherein a width of the first insulating pattern in the second direction is greater than a width of the second contact plug in the second direction.

6. The nonvolatile memory device of claim 1 , wherein a length of the first insulating pattern in the first direction is smaller than a length of the first contact plug in the first direction.

7. The nonvolatile memory device of claim 1 , further comprising:
a third contact plug penetrating the first insulating pattern, extending in the first direction, and spaced apart from the first contact plug in the second direction;
a fourth contact plug penetrating the insulating layer, extending in the first direction, spaced apart from the second contact plug in the second direction, and connected to the third contact plug; and
a second input/output pad connected to the fourth contact plug and electrically connected to the circuit element.

8. The nonvolatile memory device of claim 7 , wherein the first and third contact plugs are in the first insulating pattern, and
the second and fourth contact plugs are in the insulating layer.

9. The nonvolatile memory device of claim 1 , further comprising a dummy contact plug penetrating the first insulating pattern, extending in the first direction, and spaced apart from the first contact plug in the second direction.

10. The nonvolatile memory device of claim 9 , wherein the dummy contact plug is not in contact with the second contact plug.

11. The nonvolatile memory device of claim 1 , further comprising:
a second insulating pattern in the substrate and spaced apart from the first insulating pattern;
a third contact plug penetrating the second insulating pattern and extending in the first direction;
a fourth contact plug penetrating the insulating layer, extending in the first direction, and connected to the third contact plug; and
a second input/output pad connected to the fourth contact plug and electrically connected to the circuit element.

12. A nonvolatile memory device comprising:
a peripheral circuit region including a plurality of circuit elements and including a lower bonding metal connected to the plurality of circuit elements; and
a cell region electrically connected to the plurality of circuit elements and including a memory element for storing data, and including an upper bonding metal connected to the memory element,
wherein the peripheral circuit region includes:
a substrate including a first surface and a second surface opposite to the first surface in a first direction;
the plurality of circuit elements on the first surface of the first substrate;
a metal layer on the first surface of the first substrate and connected to a part of the plurality of circuit elements;
a first insulating pattern in the first substrate;
a first insulating layer on the second surface of the first substrate;
a first contact plug penetrating the first insulating pattern, extending from the metal layer in the first direction, and connected to the metal layer;
a second contact plug penetrating the first insulating layer, extending in the first direction, and connected to the first contact plug; and
a first input/output pad on the first insulating layer and connected to the second contact plug.

13. The nonvolatile memory device of claim 12 , wherein the upper bonding metal and the lower bonding metal are bonded on a contact surface between the cell region and the peripheral circuit region.

14. The nonvolatile memory device of claim 12 , wherein the cell region includes:
a second substrate including a third surface and a fourth surface opposite to the third surface in the first direction;
a common source line on the third surface of the second substrate;
a plurality of word lines stacked on the common source line;
a second insulating pattern in the second substrate;
a second insulating layer on the fourth surface of the second substrate;
a third contact plug penetrating the second insulating pattern and extending in the first direction;
a fourth contact plug penetrating the second insulating layer, extending in the first direction, and connected to the third contact plug;
a bonding metal connected to the third contact plug and connected to at least a part of the plurality of circuit elements; and
a second input/output pad connected to the fourth contact plug and electrically connected to at least a part of the plurality of circuit elements.

15. The nonvolatile memory device of claim 14 , wherein the lower bonding metal of the peripheral circuit region is in contact with the bonding metal of the cell region.

16. The nonvolatile memory device of claim 14 , wherein the second insulating pattern is spaced apart from the plurality of word lines.

17. The nonvolatile memory device of claim 14 , wherein the bonding metal of the cell region is electrically connected to the plurality of circuit elements of the peripheral circuit region through the metal layer of the peripheral circuit region.

18. A nonvolatile memory system comprising:
a main substrate;
a nonvolatile memory device on the main substrate; and
a controller on the main substrate and electrically connected to the nonvolatile memory device,
wherein the nonvolatile memory device includes:
a first substrate including a first surface and a second surface opposite to the first surface in a first direction;
a second substrate spaced apart from the first substrate in the first direction;
a cell structure formed between the first and second substrates;
a peripheral circuit structure including a circuit element configured to drive the cell structure and is between the first and second substrates;
an insulating pattern in the first substrate;
an insulating layer on the second surface of the first substrate;
a first contact plug penetrating the insulating pattern and extending in the first direction;
a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ji Won
• Ahn Jae Ho
• Hwang Sung-Min
• Lim Joon-Sung
• Sung Suk Kang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title