Storage device and the read operating method thereof

Patent metadata

Field	Value
Publication number	US-2022020433-A1
Application number	US-202117182556-A
Country	US
Kind code	A1
Filing date	Feb 23, 2021
Priority date	Jul 17, 2020
Publication date	Jan 20, 2022
Grant date	—

Abstract

A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.

First claim

1 . A storage device comprising:
a nonvolatile memory device comprising a nonvolatile memory cell array including a string including a first memory cell and a second memory cell stacked sequentially in a first direction, and an OTP memory cell array configured to store reference count values, the first memory cell connected to a first word line and the second memory cell connected to a second word line; a controller comprising a processor configured to generate a read command for the first memory cell; and a read level generator comprising a counter configured to receive the read command and calculate an off-cell count value of memory cells connected to the second word line, and a comparator configured to receive a first reference count value from among the reference count values stored in the OTP memory cell array, compare the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determine a read level of the first memory cell based on the threshold voltage shift.

2 . The storage device of claim 1 , further comprising a voltage generator configured to send a read voltage generated based on the read level to the nonvolatile memory cell array.

3 . The storage device of claim 1 , further comprising a buffer memory, the read level generator disposed inside the buffer memory.

4 . The storage device of claim 1 , wherein the read level generator is configured to increase the read level when the off-cell count value is greater than the first reference count value.

5 . The storage device of claim 4 , wherein a difference between the increased read level and a minimum threshold voltage of a first state of the first memory cell to be read responsive to the read command is greater than or equal to an upper offset voltage.

6 . The storage device of claim 1 , wherein the read level generator is configured to reduce the read level when the off-cell count value is smaller than the first reference count value.

7 . The storage device of claim 6 , wherein a difference between the reduced read level and a maximum threshold voltage of a second state having a threshold voltage distribution lower than a first state of the first memory cell to be read responsive to the read command is greater than or equal to a lower offset voltage.

8 . The storage device of claim 1 , wherein the OTP memory cell array stores the first reference count value which is compared with the off-cell count value of the memory cells connected to the second word line, and a second reference count value which is compared with an off-cell count value of memory cells connected to the first word line.

9 . The storage device of claim 8 , wherein the first reference count value and the second reference count value are different from each other.

10 . The storage device of claim 1 , wherein the off-cell count value calculated by the counter is an off-cell count value of a state having a highest threshold voltage distribution of the memory cells connected to the second word line.

11 . The storage device of claim 1 , wherein the string includes a third memory cell disposed between the first memory cell and the second memory cell.

12 . The storage device of claim 1 , wherein the read level generator is disposed inside the controller.

13 . A storage device comprising:
a nonvolatile memory device comprising a nonvolatile memory cell array including a string including a first memory cell, a second memory cell and a string select transistor stacked sequentially in a first direction, and an OTP memory cell array including reference count values, the first memory cell connected to a first word line and the second memory cell connected to a second word line; a controller connected to the nonvolatile memory device through a voltage generator; and a read level generator configured to receive a read command for the first memory cell from the controller, generate a read level for the first memory cell, and transmit the read level to the controller, wherein the nonvolatile memory device perform a read operation of the first memory cell responsive to the read command, the read level generator comprising a counter configured to receive the read command and calculate an off-cell count value of memory cells connected to the second word line, and the read level generator further comprising a comparator configured to receive a first reference count value from among the reference count values stored in the OTP memory cell array, compare the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determine the read level of the first memory cell based on the threshold voltage shift.

14 . The storage device of claim 13 , further comprising a buffer memory, the read level generator disposed inside the buffer memory.

15 . The storage device of claim 13 , wherein the read level generator is configured to increase the read level when the off-cell count value is greater than the first reference count value, and
a difference between the increased read level and a minimum threshold voltage of a first state of the first memory cell to be read responsive to the read command is greater than or equal to an upper offset voltage.

16 . The storage device of claim 13 , wherein the read level generator is configured to reduce the read level when the off-cell count value is smaller than the first reference count value, and
a difference between the reduced read level and a maximum threshold voltage of a second state having a threshold voltage distribution lower than a first state of the first memory cell to be read responsive to the read command is greater than or equal to a lower offset voltage.

17 . The storage device of claim 13 , wherein the OTP memory cell array stores the first reference count value which is compared with the off-cell count value of the memory cells connected to the second word line, and a second reference count value which is compared with an off-cell count value of memory cells connected to the first word line,
wherein the first reference count is different from the second reference count.

18 . The storage device of claim 13 , wherein the off-cell count value calculated by the counter is an off-cell count value of a state having a highest threshold voltage distribution of the memory cells connected to the second word line.

19 . A storage device comprising:
a nonvolatile memory device comprising a nonvolatile memory cell array including a string including a first memory cell and a second memory cell stacked sequentially in a first direction, and an OTP memory cell array configured to store reference count values, the first memory cell connected to a first word line and the second memory cell connected to a second word line; a counter configured to receive a read command for the first memory cell and calculate an off-cell count value of the memory cells connected to the second word line; and a comparator configured to receive a first reference count value from among the reference count values stored in the OTP memory cell array, compare the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determine a read level of the first memory cell based on the threshold voltage shift.

20 . The storage device of claim 19 , further comprising a voltage generator configured to send a read voltage generated based on the read level to the nonvolatile memo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Jun-Ho
• Kang Suk-Eun
• Lee Do Gyeong
• Lee Ju Won

Classifications

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title