Structure and formation method of semiconductor device structure

Patent metadata

Field	Value
Publication number	US-9876117-B2
Application number	US-201715478758-A
Country	US
Kind code	B2
Filing date	Apr 4, 2017
Priority date	Aug 31, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature. The passivation layer separates the fin structure from the interfacial layer.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate, wherein the fin structure comprises a lower portion and an upper portion, and wherein the upper portion comprises a first surface and a second surface which is inclined to the first surface;
an isolation feature surrounding the lower portion of the fin structure;
a passivation layer covering the first surface and the second surface of the upper portion of the fin structure, wherein the passivation layer comprises a semiconductor material and has a substantially uniform thickness; and
an interfacial layer over the passivation layer, wherein the interfacial layer comprises the semiconductor material, and the interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature, and wherein the passivation layer separates the fin structure from the interfacial layer.

2. The semiconductor device structure as claimed in claim 1 , wherein a sum of a thickness of the first portion of the interfacial layer and the thickness of the passivation layer is substantially equal to a thickness of the second portion of the interfacial layer.

3. The semiconductor device structure as claimed in claim 1 , wherein an interface between the isolation feature and the lower portion of the fin structure is non-coplanar with the second surface of the upper portion of the fin structure.

4. The semiconductor device structure as claimed in claim 1 , wherein the passivation layer is in contact with the first surface and the second surface of the fin structure.

5. The semiconductor device structure as claimed in claim 1 , wherein the interfacial layer adjoins the passivation layer and the isolation feature.

6. The semiconductor device structure as claimed in claim 1 , wherein the passivation layer is substantially free of oxygen.

7. The semiconductor device structure as claimed in claim 1 , further comprising a gate dielectric layer, wherein the first portion of the interfacial layer is between the passivation layer and the gate dielectric layer, and the second portion of the interfacial layer is between the isolation feature and the gate dielectric layer.

8. A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate, wherein an upper portion of the fin structure comprises a first surface and a second surface which is inclined to the first surface;
a passivation layer covering the first surface and the second surface of the fin structure, wherein the passivation layer has a substantially uniform thickness;
an isolation feature surrounding a lower portion of the fin structure, wherein an interface between the isolation feature and the lower portion of the fin structure is non-coplanar with the first surface and the second surface of the fin structure; and
a dielectric layer covering the passivation layer and the isolation feature.

9. The semiconductor device structure as claimed in claim 8 , further comprising an interfacial layer, wherein the interfacial layer has a first portion sandwiched between the passivation layer and the dielectric layer and a second portion sandwiched between the isolation feature and the dielectric layer.

10. The semiconductor device structure as claimed in claim 9 , wherein a thickness of the first portion of the interfacial layer is less than a thickness of the second portion of the interfacial layer.

11. The semiconductor device structure as claimed in claim 9 , wherein the interfacial layer comprises an oxide containing oxygen and a semiconductor material, and the passivation layer is made of the semiconductor material.

12. The semiconductor device structure as claimed in claim 8 , wherein a distance between the upper portion of the fin structure and the dielectric layer is greater than a distance between the isolation feature and the dielectric layer.

13. The semiconductor device structure as claimed in claim 8 , wherein a width of the upper portion of the fin structure is less than a width of the lower portion of the fin structure, and wherein the passivation layer adjoins the interface between the isolation feature and the lower portion of the fin structure.

14. The semiconductor device structure as claimed in claim 8 , wherein the passivation layer surrounds the upper portion of the fin structure and is separated from the lower portion of the fin structure by the isolation feature.

15. A method for forming a semiconductor device structure, comprising:
forming a fin structure over a semiconductor substrate, wherein the fin structure comprises a lower portion and an upper portion, and wherein the upper portion comprises a first surface and a second surface which is inclined to the first surface;
forming an isolation feature surrounding the lower portion of the fin structure;
forming an interfacial layer comprising an oxide containing oxygen and a semiconductor material, wherein the interfacial layer covers the fin structure and the isolation feature;
forming an oxygen scavenging layer over the interfacial layer, wherein the oxygen scavenging layer covers the fin structure and the isolation feature; and
performing a thermal process such that the oxygen scavenging layer draws out the oxygen from a first portion of the interfacial layer adjoining the fin structure, wherein the first portion of the interfacial layer is reduced to form a passivation layer comprising the semiconductor material during the thermal process.

16. The method for forming a semiconductor device structure as claimed in claim 15 , wherein the first portion of the interfacial layer becomes thinner during the thermal process, and wherein a second portion of the interfacial layer adjoining the isolation feature keeps substantially the same thickness during the thermal process.

17. The method for forming a semiconductor device structure as claimed in claim 15 , wherein the upper portion of the fin structure becomes narrower and shorter during the thermal process.

18. The method for forming a semiconductor device structure as claimed in claim 15 , further comprising:
forming a barrier layer covering the oxygen scavenging layer before the thermal process; and
removing the barrier layer to expose the oxygen scavenging layer after the thermal process.

19. The method for forming a semiconductor device structure as claimed in claim 18 , further comprising:
forming a second fin structure over the semiconductor substrate before the formation of the interfacial layer, wherein the interfacial layer, the oxygen scavenging layer and the barrier layer further cover the second fin structure; and
etching the barrier layer such that the barrier layer covers the fin structure and exposes the second fin structure during the thermal process, wherein the interfacial layer is in contact with the second fin structure after the thermal process.

20. The method for forming a semiconductor device structure as claimed in claim 15 , further comprising:
performing a surface treatment over the fin structure to form —H bonds on the first surface and the second surface of the upper portion of the fin structure before the formation of the interfacial layer; and
forming —OH bonds on the first surface and the second surface of the upper portion of the fin structure after the surface treatment and before the thermal process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Cheng-Yi
• Yeh Chih-Chieh
• Chiang Hung-Li
• Chen Hung-Ming
• Yeo Yee-Chia

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H01L29/0649

  Electricity · mapped topic