Methods of forming PMOS and NMOS FinFET devices on CMOS based integrated circuit products

Patent metadata

Field	Value
Publication number	US-9799767-B2
Application number	US-201514940597-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.

First claim

What is claimed:

1. A method of forming PMOS and NMOS FinFET devices for a CMOS integrated circuit product formed on a semiconductor substrate made of a first semiconductor material, the method comprising:
forming a first fin for said PMOS device and a second fin for said NMOS device, each of said first and second fins comprising a lower substrate fin portion made of said first semiconductor material and an upper fin portion that is positioned above said lower substrate fin portion, wherein said upper fin portion of said first and second fins is made of a semiconductor material that is different from said first semiconductor material;
performing at least one process operation to form a recessed layer of insulating material adjacent said first and second fins, said recessed layer of insulating material comprising a recessed upper surface that exposes at least a first portion of said upper fin portion of said first fin and exposes at least a first portion of said upper fin portion of said second fin;
forming a first patterned masking layer that covers said at least said first portion of said upper fin portion of said first fin of said PMOS device and exposes said at least said first portion of said upper fin portion of said second fin of said NMOS device;
with said first patterned masking layer in position, performing an epitaxial deposition process to form a semiconductor material cladding on said at least said exposed first portion of said upper fin portion of said second fin for said NMOS device, wherein said semiconductor material cladding is a different semiconductor material than that of said semiconductor material of said upper fin portion of said second fin;
removing said first patterned masking layer to re-expose said at least said first portion of said upper fin portion of said first fin of said PMOS device;
forming a PMOS gate structure for said PMOS FinFET device around and in direct contact with said at least said re-exposed first portion of said upper fin portion of said first fin of said PMOS device; and
forming an NMOS gate structure for said NMOS FinFET device around said semiconductor material cladding.

2. The method of claim 1 , wherein said first semiconductor material is silicon, said semiconductor material of said upper fin portions of said first and second fins comprises silicon-germanium (Si (1-x )Ge x where “x” ranges from 0.1-1), substantially pure germanium, or a III-V material, and said semiconductor material cladding comprises silicon-germanium (Si (1-x )Ge x where “x” ranges from 0.1-1) or silicon.

3. The method of claim 1 , wherein said first semiconductor material is silicon, said semiconductor material of said upper fin portions of said first and second fins comprises silicon-germanium (Si (1-x )Ge x where “x” ranges from 0.1-1), and said semiconductor material cladding is silicon.

4. The method of claim 1 , wherein said first semiconductor material is silicon, said semiconductor material of said upper fin portions of said first and second fins is silicon-germanium and said semiconductor material cladding is silicon-germanium with a germanium concentration that is greater than a germanium concentration of said semiconductor material of said upper fin portions of said first and second fins.

5. The method of claim 1 , wherein said semiconductor material of said upper fin portions of said first and second fins is formed with a compressive stress.

6. The method of claim 5 , wherein said semiconductor material cladding is formed with a tensile stress.

7. The method of claim 1 , wherein said first semiconductor material and said semiconductor material cladding are made of a same semiconductor material.

8. The method of claim 1 , wherein said first semiconductor material, said semiconductor material of said upper fin portions of said first and second fins, and said semiconductor material cladding are each different semiconductor materials.

9. The method of claim 1 , wherein performing said epitaxial deposition process to form said semiconductor material cladding comprises performing said epitaxial deposition process to form a conformal layer of said semiconductor material cladding having a substantially uniform thickness on said exposed upper portion of said second fin for said NMOS device.

10. A method of forming PMOS and NMOS FinFET devices for a CMOS integrated circuit product formed on a semiconductor substrate made of a first semiconductor material, the method comprising:
forming a first fin for said PMOS device and a second fin for said NMOS device, each of said first and second fins comprising said first semiconductor material;
forming a layer of insulating material in a plurality of fin-formation trenches defined in said substrate adjacent said first and second fins;
performing a first common recess etching process on both said first and second fins to define a first recessed fin with a first recessed fin cavity located above said first recessed fin and a second recessed fin with a second recessed fin cavity located above said second recessed fin;
performing a first epitaxial deposition process to form a second semiconductor material in said first and second fin cavities on said recessed first and second fins, wherein said second semiconductor material is a semiconductor material that is different from said first semiconductor material;
performing at least one recess etching process on said layer of insulating material to expose at least a first portion of said second semiconductor material formed above said recessed first fin and to expose at least a first portion of said second semiconductor material formed above said recessed second fin;
forming a first patterned masking layer that covers said at least said first portion of said second semiconductor material formed above said recessed first fin of said PMOS device and exposes said at least said first portion of said second semiconductor material formed above said recessed second fin of said NMOS device;
with said first patterned masking layer in position, performing a second epitaxial deposition process to form semiconductor material cladding on said at least said exposed first portion of said second semiconductor material formed above said recessed second fin for said NMOS device, wherein said semiconductor material cladding is a different semiconductor material than said second semiconductor material;
removing said first patterned masking layer to re-expose said at least said first portion of said second semiconductor material formed above said recessed first fin of said PMOS device;
forming a PMOS gate structure for said PMOS FinFET device around and in direct contact with said at least said re-exposed first portion of said second semiconductor material formed above said recessed first fin of said PMOS device; and
forming an NMOS gate structure for said NMOS FinFET device around said semiconductor material cladding.

11. The method of claim 10 , wherein said first semiconductor material is silicon, said second semiconductor material comprises silicon-germanium (Si (1-x )Ge x where “x” ranges from 0.1-1), substantially pure germanium, or a III-V material and said semiconductor material cladding comprises (Si (1-x )Ge x where “x” ranges from 0.1-1) or silicon.

12. The method of claim 10 , wherein said first semiconductor material is silicon, said second semiconductor material comprises silicon-germanium (Si (1-x )Ge x where “x” ranges from 0.1-1), and said semiconductor material cladding is silicon.

13. The method of claim 10 , wherein said first semiconductor material is silicon, said second semiconductor material is silicon-germanium with a first germanium conc

Assignees

• Globalfoundries Inc

Inventors

• Jacob Ajey Poovannummoottil

Classifications

• H01L21/823878

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic