Semiconductor device and fabrication method therefor

Patent metadata

Field	Value
Publication number	US-11715639-B2
Application number	US-201715701680-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Nov 29, 2016
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
depositing a silicon layer over a substrate;
depositing a dielectric layer over the silicon layer;
removing a portion of the silicon layer and the dielectric layer to form a gate stack, wherein the gate stack includes the dielectric layer over the silicon layer;
performing a hydrogen treatment on the gate stack, wherein the hydrogen treatment is configured to induce a migration of silicon atoms, and the hydrogen treatment is performed at a temperature of about 400 degrees Celsius;
forming spacers along sidewalls of the gate stack following performing the hydrogen treatment; and
removing the gate stack following the hydrogen treatment, wherein removing the gate stack comprises removing the entirety of the silicon layer.

2. The method of claim 1 , wherein performing the hydrogen treatment comprises:
raising a chamber temperature to a temperature ranging from about 400 degrees Celsius to about 1200 degrees Celsius.

3. The method of claim 1 , wherein performing the hydrogen treatment comprises:
adjusting a chamber pressure to a pressure ranging from about 50 Torr to about 760 Torr.

4. The method of claim 1 , wherein performing the hydrogen treatment comprises:
treating the gate stack for a duration ranging from about 5 seconds to about 1 hour.

5. The method of claim 1 , wherein depositing the silicon layer comprises:
depositing an amorphous silicon layer or a polysilicon layer over the substrate.

6. The method of claim 1 , wherein performing the hydrogen treatment comprises:
performing the hydrogen treatment in an atmosphere containing about 1% to about 10% of a hydrogen-containing gas.

7. The method of claim 1 , wherein performing the hydrogen treatment comprises:
exposing the gate stack to hydrogen, triatomic hydrogen or silane(s).

8. The method of claim 1 , wherein performing the hydrogen treatment comprises:
raising a chamber temperature to a temperature of about 400 degrees Celsius.

9. The method of claim 1 , further comprising:
depositing an inter-layer dielectric (ILD) over the gate stack, the spacers and the substrate;
wherein the removing of the gate stack forms an opening in the ILD; and
filling the opening with a dielectric material and a metallic material.

10. The method of claim 1 , further comprising:
adding germanium atoms during the depositing of the silicon layer.

11. A method of manufacturing a semiconductor integrated circuit (IC), comprising:
forming a dielectric layer over a fin structure;
depositing an amorphous silicon layer over the dielectric layer;
depositing a hard mask layer over the amorphous silicon layer;
patterning the hard mask layer;
removing a portion of the amorphous silicon layer and a portion of the dielectric layer to form a first stack structure and a second stack structure;
performing a hydrogen treatment on the first stack structure and the second stack structure, wherein the hydrogen treatment includes an annealing process or a plasma process, the hydrogen treatment is configured to induce a migration of silicon atoms, and the hydrogen treatment is performed at a temperature of about 400 degrees Celsius;
removing at least one of the first stack structure or the second stack structure following the hydrogen treatment, wherein removing the at least one of the first stack structure or the second stack structure comprises removing the entirety of the amorphous silicon layer;
performing the hydrogen treatment with the hard mask layer over the first stack structure; and
forming spacers along sidewalls of the first stack structure after performing the hydrogen treatment.

12. The method of claim 11 , wherein performing the hydrogen treatment comprises:
performing a hydrogen thermal annealing treatment at a temperature ranging from about 400 degrees Celsius to about 1200 degrees Celsius for a duration ranging from about 5 seconds to about 1 hour.

13. The method of claim 11 , wherein performing the hydrogen treatment comprises:
performing a hydrogen plasma treatment at a radio frequency (RF) power ranging from about 200 watts to about 800 watts for a duration ranging from about 5 seconds to about 300 seconds.

14. The method of claim 11 , further comprising:
depositing the amorphous silicon layer over an isolation feature; and
removing another portion of the amorphous silicon layer and another portion of the dielectric layer to form a third stack structure.

15. The method of claim 14 , further comprising:
forming source/drain features at opposite sides of the first stack structure, wherein opposite sides of the second stack structure and opposite sides of the third stack structure are free of source/drain features.

16. The method of claim 14 , further comprising:
forming an etch stop layer over the first stack structure, source/drain features between the first stack structure and the second stack structure, the second stack structure, and the third stack structure;
depositing an inter-layer dielectric (ILD) over the etch stop layer; and
planarizing the dielectric layer.

17. The method of claim 16 , further comprising:
removing the first stack structure from the ILD to form a first opening; and
filling the first opening with a dielectric layer and a conductive layer.

18. The method of claim 16 , further comprising:
removing the second stack structure from the ILD to form a second opening; and
filling the second opening with a dielectric layer and a conductive layer.

19. The method of claim 16 , further comprising:
removing the third stack structure from the ILD to form a third opening; and
filling the third opening with a dielectric layer and a conductive layer.

20. A method of manufacturing a semiconductor structure, comprising:
depositing a silicon layer over a substrate;
depositing a plurality of dielectric layers over the silicon layer;
removing a portion of the silicon layer to form a gate stack, wherein the gate stack includes the plurality of dielectric layers;
performing a hydrogen treatment on the gate stack including the plurality of dielectric layers, wherein the hydrogen treatment reduces voids in the gate stack, and the hydrogen treatment is performed at a temperature of about 400 degrees Celsius;
forming spacers along sidewalls of the gate stack after performing the hydrogen treatment; and
removing the entirety of the silicon layer in the gate stack to define an opening between the spacers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sie Yuan-Chun
• Tseng Po-Yi
• Chen Chien-Hao
• Lai Ching-Lun
• Sung David
• Hsieh Ming-Feng
• Huang Yi-Chi

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title