Passivated germanium-on-insulator lateral bipolar transistors

Patent metadata

Field	Value
Publication number	US-9852938-B1
Application number	US-201615231087-A
Country	US
Kind code	B1
Filing date	Aug 8, 2016
Priority date	Aug 8, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

After forming an epitaxial germanium layer over a germanium-on-insulator substrate including an insulator layer and a doped germanium layer overlying the insulator layer, the doped germanium layer is selectively removed and a passivation layer is formed within a space between the epitaxial germanium layer and the insulator layer that is formed by removal of the doped germanium layer. A lateral bipolar transistor is subsequently formed in the epitaxial germanium layer.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a passivation layer located on an insulator layer;
an epitaxial germanium portion located on the passivation layer and including an intrinsic base region comprising dopants of a first conductivity type, an emitter region laterally contacting a first side of the intrinsic base region and comprising dopants of a second conductivity type that is the opposite type of the first conductivity type, and a collector region laterally contacting a second side of the intrinsic base region opposite the first side and comprising dopants of the second conductivity type;
an extrinsic base region vertically contacting the intrinsic base region and comprising dopants of the first conductivity type; and
a trench isolation structure laterally surrounding the passivation layer and the doped epitaxial germanium portion.

2. The semiconductor structure of claim 1 , wherein the passivation layer comprises aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, tantalum oxynitride, aluminum nitride, hafnium oxide, hafnium nitride, or germanium oxide.

3. The semiconductor structure of claim 1 , wherein an entirety of the passivation layer contacts a bottom surface of the epitaxial germanium portion.

4. The semiconductor structure of claim 1 , further comprising a dielectric spacer located on sidewalls of the extrinsic base region.

5. The semiconductor structure of claim 1 , further comprising a dielectric base cap located on the extrinsic base region.

6. The semiconductor structure of claim 1 , wherein the extrinsic base region comprises doped silicon, a doped silicon-germanium alloy, a doped silicon-carbon alloy, or a doped silicon-germanium-carbon alloy.

7. The semiconductor structure of claim 1 , wherein the extrinsic base region has a dopant concentration greater than a dopant concentration of the intrinsic base region.

8. The semiconductor structure of claim 1 , wherein the epitaxial germanium portion comprises single crystalline germanium.

9. A semiconductor structure comprising:
a passivation layer located on an insulator layer;
an epitaxial germanium portion located on the passivation layer and including an intrinsic base region comprising dopants of a first conductivity type, an emitter region laterally contacting a first side of the intrinsic base region and comprising dopants of a second conductivity type that is the opposite type of the first conductivity type, and a collector region laterally contacting a second side of the intrinsic base region opposite the first side and comprising dopants of the second conductivity type; and
an extrinsic base region vertically contacting the intrinsic base region and comprising dopants of the first conductivity type,
wherein the passivation layer contacts sidewalls and a bottom surface of the epitaxial germanium portion.

10. A method of forming a semiconductor structure comprising:
providing a germanium-on-insulator (GOI) substrate comprising, from bottom to top, a handle substrate, a buried insulator layer and a doped germanium layer;
forming an epitaxial germanium layer on the doped germanium layer;
forming a trench extending through the epitaxial germanium layer and the doped germanium layer, the trench exposing sidewalls of a doped germanium portion and an epitaxial germanium portion;
removing the doped germanium portion, wherein a space is formed between the epitaxial germanium portion and the buried insulator layer; and
forming a passivation layer to fill the space.

11. The method of claim 10 , wherein the passivation layer comprises aluminum oxide, silicon dioxide, silicon nitride, silicon oxynitride, tantalum oxynitride, aluminum nitride, hafnium nitride, or germanium oxide.

12. The method of claim 10 , further comprising:
forming a hard mask layer on a top surface of the epitaxial germanium layer;
patterning the hard mask layer to provide a hard mask portion; and
patterning the epitaxial germanium layer and the doped germanium layer using the hard mask portion as an etch mask, wherein the trench exposes sidewalls of the hard mask portion.

13. The method of claim 12 , further comprising filling the trench with a dielectric material to provide an isolation structure.

14. The method of claim 13 , further comprising removing the hard mask portion from a top surface of the epitaxial germanium portion.

15. The method of claim 10 , wherein the forming the passivation layer is performed by atomic layer deposition or chemical vapor deposition.

16. The method of claim 10 , wherein the forming the passivation layer is performed by oxidation of portions of the epitaxial germanium layer exposed by the space and the trench.

17. The method of claim 10 , wherein the passivation layer has a same thickness as the doped germanium portion.

18. The method of claim 10 , further comprising forming an intrinsic base region comprising dopants of a first conductivity type and regions comprising dopants of a second conductivity that is the opposite type of the first conductivity type in the epitaxial germanium portion and forming an extrinsic base region comprising dopants of the first conductivity type overlying the base region.

19. The method of claim 18 , further comprising forming a dielectric spacer on sidewalls of the extrinsic base region.

Assignees

• IBM

Inventors

• Chan Kevin K
• Ning Tak H
• Yau Jeng-Bang

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title