Unit for a bus system, master-slave bus system with a plurality of units, and method for addressing units of a bus system

Patent metadata

Field	Value
Publication number	US-11714768-B2
Application number	US-202117399620-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 13, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.

First claim

The invention claimed is:

1. A unit for a bus system having:
a bus interface;
a control input for receiving an input signal and a control output for sending an output signal;
wherein the control input is connected to an input circuit for processing the input signal and the control output is connected to an output circuit for generating the output signal;
an address memory, which is embodied to store a collective broadcast address and an individual unit address;
and wherein the output circuit is embodied to generate the signal that is present at the control output from a supply voltage of the unit or from an external voltage.

2. The unit according to claim 1 ,
wherein the unit is a slave unit of a master/slave bus system and the unit address is a slave address.

3. The unit according to claim 1 ,
wherein the address memory is embodied to store the collective broadcast address, the individual unit address, and a collective allocation address.

4. The unit according to claim 1 ,
wherein the input circuit, the output circuit, the control input, and the control output are separated from one another on a circuitry level and/or are connected to one another only by way of a higher-level control logic of the unit.

5. The unit according to claim 1 ,
wherein the control input is a digital input and the input circuit is embodied to process a digital signal that is present at the control input
or wherein the control input is an analog input and the input circuit is embodied to process an analog signal that is present at the control input.

6. The unit according to claim 1 ,
wherein the control output is a digital output and the output circuit is embodied to generate a digital signal that is present at the control output
or wherein the control output is an analog output and the output circuit is embodied to generate an analog signal that is present at the control output
or wherein the control output is an open collector and the output circuit is embodied to generate a digital signal that is present at the control output.

7. The unit according to claim 1 ,
further comprising a voltage output that is configured to be connected directly to the control input
or also having a voltage output that is configured to be or is connected to the control input via a potentiometer or via a switch.

8. The unit according to claim 1 ,
the unit operable
to switch from an operating mode into an addressing mode upon receipt of an addressing command addressed to the broadcast address via the bus interface or upon receipt of another signal, and
in the addressing mode, to generate an inhibiting signal with the output circuit and to send the inhibiting signal as an output signal at the control output, and, upon receipt of an enable signal at the control input, to switch from the addressing mode into an allocation mode,
in the allocation mode, to store an address, which has been received via the bus interface, as an individual unit address in the address memory and after the storage of the unit address, to switch from the allocation mode into a wait mode,
in the wait mode, to generate an enable signal with the output circuit and to send the enable signal as an output signal at the control output.

9. The unit according to claim 8 ,
further comprising an inhibition circuit,
wherein by way of the inhibition circuit, the unit is embodied
so that it can be switched into the allocation mode only if the control output sends the inhibiting signal and the enable signal is present at the control input.

10. A master/slave bus system with a master and a plurality of units according to claim 1 functioning as slave units,
wherein the master is connected by way of at least one bus line to the units of the plurality of units
and wherein respective pairs of units of the plurality of units are connected to each other by way of a control line, which connects the control output of a first unit to the control input of a second unit so that each of the units of the plurality of units are connected to one another in series by way of the respective control lines.

11. The master/slave bus system according to the preceding claim 10 ,
wherein the control output of a last unit of the units that are connected to one another in series is connected to the master by way of a last control line.

12. The master/slave bus system according to claim 10 ,
wherein the master is connected by way of a first control line to the control input of a first unit of the units that are connected to one another in series.

13. A method for addressing a plurality of units, which are connected via at least one bus line to a master to form a bus system,
wherein each unit of the plurality of units respectively has a bus interface for connecting to the bus line, a control input for receiving an input signal, and a control output for sending an output signal,
wherein the control input is connected to an input circuit for processing the input signal and the control output is connected to an output circuit for generating the output signal,
wherein each unit also has an address memory, which is embodied to store a collective broadcast address and an individual unit address,
and wherein respective pairs of units of the plurality of units are connected to each other by way of a control line, which connects the control output of a first unit to the control input of a second unit so that all of the units of the plurality of units are connected to one another in series by way of the respective control lines from an initial unit to a last unit,
and wherein the method comprises at least the following steps:
a. Switching of the plurality of units from an operating mode into an addressing mode,
wherein in the addressing mode, each of the units generate an inhibiting signal with the output circuit and send the inhibiting signal as an output signal at the control output so that the inhibiting signal is present at the control input of a next unit in the series;

b. Switching of the first unit of the units that are connected in series from the addressing mode into an allocation mode by transmission of an enable signal to the control input of the initial unit in the series;
c. Allocation of an address to a unit that is in the allocation mode by transmission of an address to the unit via the bus line and storage of the address as an individual unit address in the address memory;
d. After the storage of the address, switching of the unit from the allocation mode into a wait mode,
wherein in the wait mode, the output circuit of the unit generates a signal that is sent as an output signal in the form of an enable signal at the control output of the unit to the control input of the next unit in the series of units that are connected to one another, as a result of which the next unit in the series is switched into the allocation mode;

e. Repetition of steps c. and d. for each unit until all of the units of the plurality of units are in the wait mode;
f. Switching of the plurality of units from the wait mode into the operating mode.

14. The method according to claim 13 ,
wherein in order to switch units from the operating mode into the addressing mode, a bus signal is sent by the master via the bus line to all of the units.

15. The method according to claim 13 ,
wherein after the allocation of the address, the unit is switched into the wait mode automatically or by transmission of a bus signal from the master to the unit.

Assignees

• Ebm Papst Mulfingen Gmbh & Co Kg

Inventors

• Fessel Andreas
• Humm Markus

Classifications

• G06F13/362 Primary

  with centralised access control · CPC title

• G05B19/0423 Primary

  Input/output · CPC title

• H04L12/40013 Primary

  Details regarding a bus controller · CPC title

• G06F12/0653 Primary

  with centralised address assignment · CPC title

• G05B2219/21063

  Bus, I-O connected to a bus · CPC title