Circuit arrangement for universal connection of a bus participant to at least one bus

US9772966B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9772966-B2
Application numberUS-201414161064-A
CountryUS
Kind codeB2
Filing dateJan 22, 2014
Priority dateJan 22, 2013
Publication dateSep 26, 2017
Grant dateSep 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topology in such a way that the first bus output is connected at least indirectly to the second bus input and the second bus output is connected at least indirectly to the first bus input via the bus. The bus in the circuit arrangement can be separated to obtain a line topology and can be configured as bus-terminating at one of the bus inputs or bus outputs. A system for the functional testing of bus participants on a bus in a simulation environment is provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit arrangement for connecting a bus participant to at least one bus, the circuit arrangement comprising: an interface for connecting the bus participant to the circuit arrangement; a first bus input and a first bus output, between which the bus participant is switchable via the interface; and a second bus input and a second bus output for connecting the first bus to the circuit arrangement in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the first bus and the second bus output is connected at least indirectly to the first bus input via the first bus, wherein the first bus in the circuit arrangement is configured to be separated to obtain a line topology, wherein the circuit arrangement is configured as bus-terminating at one of the bus inputs or bus outputs, and wherein the circuit arrangement is adapted to be connected to a second bus and further comprises a bus changeover switch group via which the interface is selectively connectable to the first bus or to the second bus. 2. The circuit arrangement according to claim 1 , wherein the interface is connectable via a first switch group to the first bus input and the first bus output or the second bus input and the second bus output, and wherein the connection from the first switch group to the second bus input and to the second bus output is severable by a disconnect switch group in order to change the ring topology of the first bus to a line topology. 3. The circuit arrangement according to claim 2 , further comprising a termination unit for the electrical termination of the first bus, which, depending on a position of the disconnect switch group, is connectable to the second bus input and/or the second bus output via at least one termination switch. 4. The circuit arrangement according to claim 2 , wherein the disconnect switch groups comprise double-throw switches and selectively connect the second bus input and/or the second bus output to the first switch group or to a bypass line. 5. The circuit arrangement according to claim 1 , further comprising a bridging switch group for direct connection of the first bus input to the first bus output. 6. The circuit arrangement according to claim 1 , wherein the interface is connectable to the first switch group via an activation switch group for coupling and decoupling the bus participant to or from the first bus. 7. The circuit arrangement according to claim 6 , wherein the activation switch group has a switch pair for each line of the first bus, and wherein the switch pairs are switchable independently of one another. 8. The circuit arrangement according to claim 1 , wherein the second bus comprises a first bus input, a first bus output, a second bus input, and a second bus output such that the second bus is placeable in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the second bus and the second bus output is connected at least indirectly to the first bus input via the second bus. 9. The circuit arrangement according to claim 1 , further comprising a second switch group via which the interface in the position selecting the second bus of the bus changeover switch group is selectively connectable to the first bus input and the first bus output or to the second bus input and the second bus output of the second bus. 10. The circuit arrangement according to claim 9 , wherein the connection from the second switch group to the second bus input and to the second bus output of the second bus is adapted to be severed in each case by a disconnect switch group in order to change the ring topology of the second bus to a line topology, and further comprising a second termination unit for the electrical termination of the second bus, which, depending on the position of the disconnect switch groups, is connectable to the second bus input or the second bus output via at least one termination switch. 11. The circuit arrangement according to claim 10 , wherein the disconnect switch groups each comprise double-throw switches and the second bus input and/or connect the second bus output of the second bus selectively to the second switch group or to another bypass line. 12. The circuit arrangement according to claim 1 , further comprising a bridging switch group for the direct connection of the first bus input to the first bus output of the first bus and/or a bridging switch group for the direct connection of the first bus input to a first bus output of the second bus. 13. The circuit arrangement according to claim 1 , wherein the first and/or the second bus are realized as dual-wire, and wherein a first switch group and/or a second switch group and a disconnect switch groups each comprise a switch for each of the two bus lines. 14. The circuit arrangement according to claim 3 , wherein the termination unit and/or a second termination unit are formed by a termination resistor, which is switchable via a respective termination switch between the lines of a respective bus. 15. The circuit arrangement according to claim 3 , wherein the termination unit and/or a second termination unit are formed by two termination resistors, which together are connected to a ground via a capacitor, and wherein the one termination resistor is connectable to one of the first bus lines via a termination switch and the other termination resistor to the other bus line via another termination switch. 16. A system for the functional testing of bus participants on a bus in a simulation environment, the system comprising: a plurality of circuit arrangements; and a first bus, wherein the bus participants are each connectable to the first bus via an interface in each of the circuit arrangements; and a simulator unit for simulating control signals on the first bus, wherein each of the circuit arrangements has a first and a second bus input and a first and a second bus output and the first bus connects the circuit arrangements in a ring topology such that each first bus output of one of the circuit arrangements is connectable either to the first bus input of the next circuit arrangement or to the second bus input of its own circuit arrangement, wherein each second bus output of one of the circuit arrangements is connectable either to the second bus input of the next circuit arrangement or to the first bus input of its own circuit arrangement, and wherein the first bus in each of the circuit arrangements is separated to obtain a line topology and each circuit arrangement is configured as bus-terminating at one of the bus inputs or bus outputs of the first bus, and wherein the interface is a separate contact from the first bus input, the first bus output, the second bus input, and the second bus output. 17. The system according to claim 16 , wherein a second bus connects to the circuit arrangements in the same way as the first bus. 18. The system according to claim 16 , wherein each of the circuit arrangements comprises: the interface for connecting the bus participant to the circuit arrangement; a first bus input and a first bus output, between which the bus participant is switchable via the interface; and a second bus input and a second bus output for connecting the first bus to the circuit arrangement in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the first bus and the second bus output is connected at least indirectly to the first bus input via the first bus, wherein the first bus in the circui

Assignees

Inventors

Classifications

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • Loop networks · CPC title

  • Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654) · CPC title

  • Details regarding a bus interface enhancer · CPC title

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What does patent US9772966B2 cover?
A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topolo…
Who is the assignee on this patent?
Dspace Gmbh
What technology area does this patent fall under?
Primary CPC classification G06F13/4022. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).