Current mode control modulator including ramp signal generator providing slope compensation

Patent metadata

Field	Value
Publication number	US-11711071-B2
Application number	US-202117515550-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Dec 4, 2019
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A current mode control modulation includes a ramp signal generator generating a slope compensated ramp signal with slope compensation. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator includes a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit to generate the ramp signal with slope compensation.

First claim

What is claimed is:

1. A current mode control modulator generating a pulse width modulation (PWM) signal in response to a feedback voltage signal indicative of a regulated output voltage generated from an input voltage, the current mode control modulator comprising:
a first error amplifier receiving the feedback voltage signal indicative of the regulated output voltage and a target voltage, the first error amplifier generating a signal indicative of a difference between the feedback voltage signal and the target voltage on an output terminal;
a modulating comparator having a first input terminal receiving the signal indicative of the difference and a second input terminal receiving a current loop signal indicative of an expected current level, the modulating comparator having an output terminal generating a reset signal;
a latch circuit having a reset input terminal coupled to receive the reset signal from the modulating comparator, a set input terminal coupled to receive a clock signal, and an output terminal generating the PWM signal, the PWM signal having an on-duration defining a duty cycle of the PWM signal and an off-duration, wherein the set signal initiates the on-duration of the PWM signal and the reset signal terminates the on-duration of the PWM signal; and
a ramp signal generator circuit receiving the PWM signal and generating a slope compensated ramp signal as the current loop signal, the ramp signal generator comprising a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit, wherein the ramp signal generator generates the slope compensated ramp signal having a first ramp portion by using the switched capacitor circuit to divide a charge associated with the expected current level during a first duration of the PWM signal, and the ramp signal generator further generates the slope compensated ramp signal having a second ramp portion by using the switched capacitor circuit to accumulate the charge associated with the expected current level during a second duration of the PWM signal.

2. The current mode control modulator of claim 1 , wherein the first duration of the PWM signal comprises one of the on-duration or the off-duration of the PWM signal and the second duration of the PWM signal comprises the other one of the on-duration or the off-duration of the PWM signal.

3. The current mode control modulator of claim 1 , wherein the switched capacitor circuit of the ramp signal generator circuit comprises a first capacitor switchably connected to a second capacitor and supplied by the current circuit to charge or discharge the first and second capacitors, and wherein the ramp signal generator generates the first ramp portion of the slope compensated ramp signal by dividing the charge associated with the expected current level among the first capacitor and the second capacitor during the first duration of the PWM signal, the first capacitor being disconnected from the second capacitor and providing the first ramp portion of the slope compensated ramp signal, and the ramp signal generator generates the second ramp portion of the slope compensated ramp signal by accumulating and sharing the charge associated with the expected current level between the first capacitor and the second capacitor during the second duration of the PWM signal, the first capacitor being connected to the second capacitor and the first and second capacitors providing the second ramp portion of the slope compensated ramp signal.

4. The current mode control modulator of claim 3 , wherein in the switched capacitor circuit of the ramp signal generator circuit,
the first capacitor is coupled between a first node and a second node, the second node being biased to a reference voltage and the first node providing the slope compensated ramp signal;
the second capacitor is coupled between a third node and the second node; and
a first switch is coupled between the first node and the third node, the first switch being controlled by a first signal indicative of the PWM signal, the first switch being open during the first duration of the PWM signal and the first switch being closed during the second duration of the PWM signal.

5. The current mode control modulator of claim 4 , wherein the ramp signal generator further comprises the current circuit coupled to the first node and the third node and controlled by a second signal indicative of the pulse-width modulation signal to charge or discharge the first and third nodes.

6. The current mode control modulator of claim 4 , wherein the ramp signal generator further comprises a resistor coupled between the first node and the second node.

7. The current mode control modulator of claim 4 , wherein the current mode control modulator comprises a peak current mode buck modulator and the current circuit of the ramp signal generator circuit further comprises:
a first current source coupled to the first node through a second switch to provide a current proportional to the input voltage to the first node to charge the first capacitor, the second switch being controlled by a second signal indicative of the PWM signal;
a second current source coupled to the third node through a third switch to provide a current proportional to the input voltage to the third node to charge the second capacitor, the third switch being controlled by a third signal indicative of the PWM signal; and
a first current sink providing a current proportional to two times the regulated output voltage to the third node to discharge the third node,
wherein the first signal is an inverse of the PWM signal and the second and third signals are inverse of the first signal, the first duration of the PWM signal being the on-duration of the PWM signal and the second duration being the off-duration of the PWM signal, and
wherein in response to the first switch being open and the second and third switches being closed during the on-duration of the PWM signal, the first capacitor is being charged by the first current source and the ramp signal ramps up with a slope being proportional to the input voltage while the second capacitor is being charged by the second current source and the first current sink; and in response to the first switch being closed and the second and third switches being open during the off-duration of the PWM signal, the first and second capacitors are connected and being discharged by the first current sink and the ramp signal ramps down with a slope being proportional to the regulated output voltage.

8. The current mode control modulator of claim 7 , wherein the first capacitor and the second capacitor have a capacitance ratio of 1 or a capacitance ratio other than 1, and the first current source and the second current source have a ratio of 1 or other than 1.

9. The current mode control modulator of claim 4 , wherein the current mode control modulator comprises a peak current mode boost modulator and the current circuit of the ramp signal generator circuit further comprises:
a first current source coupled to the first node to provide a current proportional to the input voltage to the first node to charge the first node;
a second current source coupled to the third node to provide a current proportional to the input voltage to the third node to charge the third node; and
a first current sink coupled to the third node through a fourth switch to provide a current proportional to two times the regulated output voltage to the third node to discharge the third node, the fourth switch being controlled by a fourth signal indicative of the pulse-width modulation signal,
wherein the first and fourth signals are inverse of the pulse-width modulation signal, the first duration being an on-duration of

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Archibald Nicholas I
• Philbrick Rhys S A
• Laur Steven P

Classifications

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K6/04

  Modifying slopes of pulses, e.g. S-correction (S-correction in television H04N3/23) · CPC title