Windowless H-bridge buck-boost switching converter

Patent metadata

Field	Value
Publication number	US-9893623-B2
Application number	US-201514719945-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	Sep 21, 2012
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p−p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p−p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

First claim

The invention claimed is:

1. A method for operating a switching converter having pairs of high and low side switching elements to provide buck and boost operating modes, the method comprising:
providing a ramp signal having a slope that is based on (1) a current sense signal that varies with a current in a switching element of the converter and on (2) a specified compensation signal;
providing an error signal that is based on a difference between a specified reference signal amplitude and an output signal amplitude from the switching converter; and
when the error signal transitions to be greater than a sum of the ramp signal and a specified voltage magnitude, increasing the ramp signal by an offset amount that is at least a sum of the specified voltage magnitude and a peak-to-peak amplitude of the ramp signal and is sufficient to transition the converter from buck mode to boost mode without transitioning through an intermediate buck-boost mode; and
when the error signal transitions to be less than a difference of the ramp signal and the specified voltage magnitude, decreasing the ramp signal by an offset amount that is at least a sum of the specified voltage magnitude and a peak-to-peak amplitude of the ramp signal and is sufficient to transition the converter from boost mode to buck mode.

2. The method of claim 1 , further comprising:
providing a mode control signal based on the current sense signal and the specified compensation signal; and
updating an on/off status of the pairs of high and low side switching elements in the switching converter using a logic circuit, the logic circuit including a first input configured to receive a result of a comparison of the ramp signal and the error signal, a second input configured to receive the mode control signal, and a third input configured to receive a clock signal, and the logic circuit including an output coupled to the switching elements.

3. The method of claim 1 , further comprising generating the specified compensation signal at a first terminal of an energy storage element, including:
charging the energy storage element using a fixed current source that is coupled with the energy storage element, and
selectively discharging the energy storage element to provide a substantially sawtooth signal waveform.

4. The method of claim 3 , further comprising updating an on/off status of at least one of the high side switching elements and at least one of the low side switching elements to operate the switching converter in a buck mode or in a boost mode according to a duty cycle signal and a periodic clock signal;
wherein the selectively discharging the energy storage element includes using a switch that is triggered by the periodic clock signal.

5. The method of claim 1 , further comprising, in the buck operating mode, providing the specified compensation signal as a time-varying sawtooth waveform signal, and in the boost operating mode, providing the specified compensation signal as a DC signal having an amplitude that corresponds to a peak-to-peak amplitude of the time-varying sawtooth waveform signal.

6. The method of claim 1 , further comprising transitioning from buck mode to boost mode, including operating the switching elements according to a first duty cycle adjacently preceding the transition, the first duty cycle being substantially about 0% or 100% duty cycle, the transitioning further including operating the switching elements according to a second duty cycle adjacently following the transition, the second duty cycle being substantially the other of 0% or 100% duty cycle.

7. The method of claim 1 , further comprising sensing the current sense signal using a sensing amplifier circuit that is coupled to source and drain terminals of one of the high side switching elements.

8. The method of claim 1 , wherein the providing the ramp signal includes providing a signal that is a sum of the current sense signal, the specified compensation signal, and a boost compensation signal, wherein the boost compensation signal is provided during ‘off’ portions of the converter's cycle.

9. A buck-boost power switching converter system with primary and secondary switching elements arranged in an H-bridge configuration with an inductor, at least one of the switching elements corresponding to an input node, and at least one of the switching elements corresponding to an output node, and the system comprising:
a ramp signal generator circuit configured to generate a ramp signal having a slope that is based on (1) a current sense signal that varies with a current in a switching element of the converter and on (2) a specified compensation signal; and
a regulation circuit configured to selectively operate the primary and secondary switching elements in a selected one of a buck converter mode or in a boost converter mode, wherein the regulation circuit includes a comparator circuit to provide an error signal based on a difference between a specified reference signal amplitude and an output signal amplitude from the switching converter system;
when the error signal transitions to be greater than a sum of the ramp signal and a specified voltage magnitude, the ramp signal generator circuit configured to increase the ramp signal by an offset amount that is at least a sum of the specified voltage magnitude and a peak-to-peak amplitude of the ramp signal and is sufficient to transition the converter from buck mode to boost mode without transitioning through an intermediate buck-boost mode; and
when the error signal transitions to be less than a difference of the ramp signal and the specified voltage magnitude, the ramp signal generator circuit configured to decrease the ramp signal by an offset amount that is at least a sum of the specified voltage magnitude and a peak-to-peak amplitude of the ramp signal and is sufficient to transition the converter from boost mode to buck mode.

10. The buck-boost power converter system of claim 9 , wherein the ramp signal generator circuit includes:
a current sense circuit that provides an output that varies with an inductor current of the inductor;
a slope compensation and/or boost offset circuit that provides one of a time-varying sawtooth signal or a DC signal;
a summing node that receives the output from the current sense circuit and at least one of the time-varying sawtooth signal and the DC signal; and
a mode change circuit that receives a signal from the summing node and, in response, provides the ramp signal based on the output from the current sense circuit and based on at least one of the time-varying sawtooth signal and the DC signal from the slope compensation and/or boost offset circuit.

11. The buck-boost power converter system of claim 10 , wherein the ramp signal generator circuit includes a switching circuit, and the switching circuit selectively provides one of two different ramp signals based on an indication of a buck or boost mode, wherein the two different ramp signals are offset from each other by a specified voltage signal amplitude.

12. The buck-boost power converter system of claim 10 , wherein the current sense circuit includes a voltage-to-current converter circuit having inputs coupled across one of the primary or secondary switching elements to sense information about a current in the element.

13. The buck-boost power converter system of claim 10 , wherein the slope compensation and/or boost offset circuit includes:
a fixed current source;
an energy storage element coupled in series with the fixed current source; and
a switch configured to selectively discharge the energy storage element according to a set signal;
wherein the set signal is selected to provid

Assignees

• Analog Devices Global

Inventors

• Tanabe Hirohisa

Classifications

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title