Slope compensation for current mode control modulator

Patent metadata

Field	Value
Publication number	US-11196409-B2
Application number	US-202017035012-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Dec 4, 2019
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

First claim

What is claimed is:

1. A ramp signal generator generating a slope compensated ramp signal for a current mode control modulator, the current mode control modulator generating a pulse-width modulation signal in response to a feedback voltage signal indicative of a regulated output voltage generated from an input voltage, the ramp signal generator comprising:
a first capacitor coupled between a first node and a second node, the second node being biased to a reference voltage and the first node providing the slope compensated ramp signal;
a second capacitor coupled between a third node and the second node; and
a first switch coupled between the first node and the third node, the first switch being controlled by a first signal indicative of the pulse-width modulation signal, the first switch being open during a first duration of the pulse-width modulation signal and the first switch being closed during a second duration of the pulse-width modulation signal,
a current circuit coupled to the first node and the third node and controlled by a second signal indicative of the pulse-width modulation signal to charge or discharge the first and third nodes,
wherein the first capacitor, the second capacitor and the first switch form a switched capacitor circuit to generate the slope compensated ramp signal;
wherein in response to the first switch being open during the first duration of the pulse-width modulation signal, the ramp signal generator generates the slope compensated ramp signal having a first ramp portion by using the switched capacitor circuit to divide a charge associated with an expected current level of a current control loop of the current mode control modulator among the first capacitor and the second capacitor during the first duration of the pulse-width modulation signal, the first capacitor being disconnected from the second capacitor and providing the first ramp portion of the slope compensated ramp signal, and
wherein in response to the first switch being closed during the second duration of the pulse-width modulation signal, the ramp signal generator generates the slope compensated ramp signal having a second ramp portion by using the switched capacitor circuit to share the charge associated with the expected current level of the current control loop of the current mode control modulator between the first capacitor and the second capacitor during the second duration of the pulse-width modulation signal, the first capacitor being connected to the second capacitor and the first and second capacitors providing the second ramp portion of the slope compensated ramp signal.

2. The ramp signal generator of claim 1 , wherein the first duration of the pulse-width modulation signal comprises one of an on-duration or an off-duration of the pulse-width modulation signal and the second duration of the pulse-width modulation signal comprises the other one of the on-duration or the off-duration of the pulse-width modulation signal.

3. The ramp signal generator of claim 1 , further comprising a resistor coupled between the first node and the second node.

4. The ramp signal generator of claim 1 , wherein the current mode control modulator comprises a peak current mode buck modulator and the current circuit of the ramp signal generator circuit further comprises:
a first current source coupled to the first node through a second switch to provide a current proportional to the input voltage to the first node to charge the first capacitor, the second switch being controlled by a second signal indicative of the pulse-width modulation signal;
a second current source coupled to the third node through a third switch to provide a current proportional to the input voltage to the third node to charge the second capacitor, the third switch being controlled by a third signal indicative of the pulse-width modulation signal; and
a first current sink providing a current proportional to two times the regulated output voltage to the third node to discharge the third node,
wherein the first signal is an inverse of the pulse-width modulation signal and the second and third signals are inverse of the first signal, the first duration being an on-duration of the pulse-width modulation signal and the second duration being an off-duration of the pulse-width modulation signal, and
wherein in response to the first switch being open and the second and third switches being closed during the on-duration of the pulse-width modulation signal, the first capacitor is being charged by the first current source and the first ramp portion of the ramp signal ramps up with a slope being proportional to the input voltage while the second capacitor is being charged by the second current source and the first current sink; and in response to the first switch being closed and the second and third switches being open during the off-duration of the pulse-width modulation signal, the first and second capacitors are connected and being discharged by the first current sink and the second ramp portion of the ramp signal ramps down with a slope being proportional to the regulated output voltage.

5. The ramp signal generator of claim 4 , wherein the first capacitor and the second capacitor have a capacitance ratio of 1 or a capacitance ratio other than 1, and the first current source and the second current source have a ratio of 1 or other than 1.

6. The ramp signal generator of claim 1 , wherein the current mode control modulator comprises a peak current mode boost modulator and the current circuit of the ramp signal generator circuit further comprises:
a first current source coupled to the first node to provide a current proportional to the input voltage to the first node to charge the first node;
a second current source coupled to the third node to provide a current proportional to the input voltage to the third node to charge the third node; and
a first current sink coupled to the third node through a fourth switch to provide a current proportional to two times the regulated output voltage to the third node to discharge the third node, the fourth switch being controlled by a fourth signal indicative of the pulse-width modulation signal,
wherein the first and fourth signals are inverse of the pulse-width modulation signal, the first duration being an on-duration of the pulse-width modulation signal and the second duration being an off-duration of the pulse-width modulation signal, and
wherein in response to the first and fourth switches being open during the on-duration of the pulse-width modulation signal, the first capacitor is being charged by the first current source and the first ramp portion of the ramp signal ramps up with a slope being proportional to the input voltage while the second capacitor is being charged by the second current source; and in response to the first and fourth switches being closed during the off-duration of the pulse-width modulation signal, the first and second capacitors are connected and being discharged by the first current sink and the second ramp portion of the ramp signal ramps down with a slope being proportional to the difference of the input voltage and the regulated output voltage.

7. The ramp signal generator of claim 6 , wherein the first capacitor and the second capacitor have a capacitance ratio other than 1, and the first current source and the second current source have a ratio other than 1.

8. The ramp signal generator of claim 1 , wherein the current mode control modulator comprises a valley current mode buck modulator and the current circuit of the ramp signal generator circuit further comprises:
a second current sink coupled to the first node to provide a current proportional to the regulated output voltage to the first node to discharge the first node;
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Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Archibald Nicholas I
• Philbrick Rhys S A
• Laur Steven P

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• H03K4/08 Primary

  having sawtooth shape · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H03K6/04

  Modifying slopes of pulses, e.g. S-correction (S-correction in television H04N3/23) · CPC title