Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11705361-B2
Application number	US-202117369714-A
Country	US
Kind code	B2
Filing date	Jul 7, 2021
Priority date	Sep 3, 2020
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer;
(b) after the (a), forming a first conductive film on the semiconductor layer;
(c) after the (b), forming a first insulating film on the first conductive film;
(d) after the (c), patterning the first conductive film and the first insulating film, thereby forming a gate pattern and a cap film;
(e) after the (d), implanting an impurity into the semiconductor layer located on both sides of the gate pattern, thereby forming a first impurity region;
(f) after the (e), forming a first sidewall spacer made of a second insulating film on a side surface of the gate pattern;
(g) after the (f), forming a second conductive film on the first impurity region so as to cover the gate pattern, the cap film, and the first sidewall spacer;
(h) after the (g), performing a polishing process to the second conductive film until the cap film is exposed;
(i) after the (h), patterning a part of the second conductive film, thereby forming a pad layer made of the remaining second conductive film;
(j) after the (i), filling a portion, from where the second conductive film has been removed, with a third insulating film; and
(k) after the (j), performing a polishing process to the cap film, the first sidewall spacer, the third insulating film, and the pad layer until the cap film is removed and the gate pattern is exposed.

2. The method of manufacturing the semiconductor device according to claim 1 , further comprising steps of:
(l) after the (k), implanting an impurity into the gate pattern and the pad layer; and
(m) after the (l), forming a silicide layer on each upper surface of the gate pattern and the pad layer.

3. The method of manufacturing the semiconductor device according to claim 1 , further comprising a step of:
(n) between the (a) and the (b), forming a trench which penetrates the semiconductor layer and the insulating layer and reaches the semiconductor substrate and filling the trench with a fourth insulating film, thereby forming an element isolation portion,
wherein the semiconductor layer, the insulating layer, and the semiconductor substrate are partitioned into a plurality of active regions by the element isolation portion,
wherein the plurality of active regions includes a first active region and a second active region which is adjacent to the first active region via the element isolation portion in a plan view, and
wherein the first impurity region formed in the semiconductor layer in the first active region and the first impurity region formed in the semiconductor layer in the second active region are connected by the same pad layer.

4. The method of manufacturing the semiconductor device according to claim 3 , wherein the third insulating film is located on the element isolation portion.

5. The method of manufacturing the semiconductor device according to claim 3 , further comprising a step of:
(o) after the (k), forming a plurality of plugs on the gate pattern and the pad layer,
wherein the plurality of active regions includes a third active region which is adjacent to the first active region via the element isolation portion in a plan view,
wherein the gate pattern in the third active region extends on the element isolation portion so as to be adjacent to the pad layer in the first active region via the first sidewall spacer in the third active region, and
wherein the plurality of plugs includes a shared contact plug connected to both of the gate pattern in the third active region and the pad layer in the first active region.

6. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the (g) further includes a step of forming a fifth insulating film on the second conductive film by a coating method, and
wherein the fifth insulating film is removed by the polishing process in the (h).

7. The method of manufacturing the semiconductor device according to claim 1 , wherein the second conductive film is made of silicon.

8. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the first insulating film and the third insulating film are made of silicon oxide, and
wherein the second insulating film is made of silicon nitride.

9. A method of manufacturing a semiconductor device comprising steps of:
(a) providing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer;
(b) after the (a), forming a first conductive film on the semiconductor layer;
(c) after the (b), forming a first insulating film on the first conductive film;
(d) after the (c), patterning the first conductive film and the first insulating film, thereby forming a gate pattern and a cap film;
(e) after the (d), implanting an impurity into the semiconductor layer located on both sides of the gate pattern, thereby forming a first impurity region;
(f) after the (e), forming a first sidewall spacer made of a second insulating film on a side surface of the gate pattern;
(g) after the (f), forming a second conductive film on the first impurity region so as to cover the gate pattern, the cap film, and the first sidewall spacer;
(h) after the (g), performing a polishing process to the second conductive film until the cap film is exposed;
(i) after the (h), patterning a part of the second conductive film, thereby forming a pad layer made of the remaining second conductive film;
(j) after the (i), filling a portion, from where the second conductive film has been removed, with a third insulating film;
(p) after the (j), making an upper surface of the pad layer recede such that the upper surface of the pad layer becomes lower than an upper surface of the gate pattern;
(q) after the (p), forming a sixth insulating film on the pad layer so as to cover the gate pattern, the cap film, and the first sidewall spacer;
(r) after the (q), performing an anisotropic etching to the sixth insulating film and the cap film, thereby removing the cap film and forming a second sidewall spacer made of the sixth insulating film on the side surface of the gate pattern;
(s) after the (r), forming a first silicide layer and a second silicide layer on the upper surface of the gate pattern and the upper surface of the pad layer exposed from the second sidewall spacer, respectively;
(t) after the (s), forming a seventh insulating film on the first silicide layer and the second silicide layer;
(u) after the (t), performing a polishing process to the seventh insulating film such that the second silicide layer formed on the upper surface of the pad layer is covered with the seventh insulating film and the first silicide layer formed on the upper surface of the gate pattern is removed;
(v) after the (u), removing the gate pattern and filling a portion, from where the gate pattern has been removed, with a metal film; and
(w) after the (v), performing a polishing process to the seventh insulating film until the second silicide layer is exposed.

10. The method of manufacturing the semiconductor device according to claim 9 , further comprising a step of:
(n) between the (a) and the (b), forming a trench which penetrates the semiconductor layer and the insulating layer and reaches the semiconductor substrate and filling the trench with a fourth insulating film, thereby forming an element isolation portion,
wherein the third insulating film is located on the element isolation portion,
wherein the semiconductor laye

Assignees

• Renesas Electronics Corp

Inventors

• Maeda Hitoshi
• Mihara Tatsuyoshi
• Shinkawata Hiroki

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title