Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9935125-B2
Application number	US-201313859297-A
Country	US
Kind code	B2
Filing date	Apr 9, 2013
Priority date	Apr 9, 2012
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a first region and a second region on a main surface;
a first insulating film formed in the first region on the semiconductor substrate;
a semiconductor layer formed on the first insulating film;
a first field effect transistor formed in the first region on the semiconductor substrate; and
a second field effect transistor formed in the second region on the semiconductor substrate,
wherein the first field effect transistor includes:
a first gate electrode formed on the semiconductor layer via a first gate insulating film; and
a pair of first source and drain regions of a first conductivity type, which are formed so as to sandwich the first gate electrode in a gate length direction of the first gate electrode,
the second field effect transistor includes:
a second gate electrode formed on the semiconductor substrate via a second gate insulating film; and
a pair of second source and drain regions of the first conductivity type, which are formed in the semiconductor substrate so as to sandwich the second gate electrode in a gate length direction of the second gate electrode,
each of the first source and drain regions has an epitaxial layer formed on the semiconductor layer,
uppermost surfaces of the first source and drain regions are positioned higher than a contact interface of the semiconductor layer with the first gate insulating film, and
uppermost surfaces of the second source and drain regions are positioned no higher than a contact interface of the semiconductor substrate with the second gate insulating film,
wherein lowermost surfaces of the epitaxial layers are positioned higher than a bottom surface of the second gate insulating film,
wherein sidewalls formed to be in contact with side surfaces of the first gate electrode cover upper surfaces of the epitaxial layers and expose an upper surface of the first gate electrode,
wherein the epitaxial layers have end portions with film thicknesses smaller than that of center portions of the epitaxial layers, and
the sidewalls cover the upper surfaces of the end portions of the epitaxial layers,
wherein the sidewalls include a second insulating film in contact with the side surfaces of the first gate electrode and a third insulating film that covers the second insulating film, and
the third insulating film covers the upper surfaces of the epitaxial layers, and is in contact with the upper surfaces of the epitaxial layers.

2. The semiconductor device according to claim 1 ,
wherein the uppermost surfaces of the first source and drain regions are positioned higher than an upper surface of the first gate insulating film, and
the uppermost surfaces of the second source and drain regions are positioned lower than an upper surface of the second gate insulating film.

3. The semiconductor device according to claim 1 ,
wherein the second gate insulating film has a film thickness larger than that of the first gate insulating film.

4. The semiconductor device according to claim 3 , further comprising:
a third field effect transistor formed in the second region,
wherein the third field effect transistor includes:
a third gate electrode formed on the semiconductor substrate via a third gate insulating film; and
a pair of third source and drain regions of the first conductivity type, which are formed in the semiconductor substrate so as to sandwich the third gate electrode in a gate length direction of the third gate electrode,
the third gate insulating film has a film thickness smaller than that of the second gate insulating film, and
upper surfaces of the third source and drain regions are positioned at a region as high as or lower than an interface between the semiconductor substrate and the third gate insulating film.

5. The semiconductor device according to claim 4 , further comprising:
a fourth field effect transistor formed in the second region,
wherein the fourth field effect transistor includes:
a fourth gate electrode formed on the semiconductor substrate via a fourth gate insulating film; and
a pair of fourth source and drain regions of the first conductivity type, which are formed so as to sandwich the fourth gate electrode in a gate length direction of the fourth gate electrode,
the fourth gate insulating film has a film thickness smaller than that of the second gate insulating film,
the fourth source and drain regions include epitaxial layers formed on the semiconductor substrate, and
upper surfaces of the fourth source and drain regions are positioned at a region higher than an interface between the semiconductor substrate and the fourth gate insulating film.

6. The semiconductor device according to claim 1 , wherein the pair of second source and drain regions of the first conductivity type are formed directly in the upper surface of the semiconductor substrate.

7. A semiconductor device comprising:
a semiconductor substrate having a first region and a second region on a main surface;
a first insulating film formed in the first region on the semiconductor substrate;
a semiconductor layer formed on the first insulating film;
a first field effect transistor formed in the first region on the semiconductor substrate; and
a second field effect transistor formed in the second region on the semiconductor substrate,
wherein the first field effect transistor includes:
a first gate electrode formed on the semiconductor layer via a first gate insulating film; and
a pair of first source and drain regions of a first conductivity type, which are formed so as to sandwich the first gate electrode in a gate length direction of the first gate electrode,
the second field effect transistor includes:
a second gate electrode formed on the semiconductor substrate via a second gate insulating film; and
a pair of second source and drain regions of the first conductivity type, which are formed in the semiconductor substrate so as to sandwich the second gate electrode in a gate length direction of the second gate electrode,
each of the first source and drain regions has an epitaxial layer formed on the semiconductor layer,
upper surfaces of the first source and drain regions are positioned at a region higher than a contact interface of the semiconductor layer with the first gate insulating film, and
upper surfaces of the second source and drain regions are positioned at a region no higher than a contact interface of the semiconductor substrate with the second gate insulating film,
wherein lowermost surfaces of the epitaxial layers are positioned higher than a bottom surface of the second gate insulating film,
wherein sidewalls formed to be in contact with side surfaces of the first gate electrode cover upper surfaces of the epitaxial layers and expose an upper surface of the first gate electrode,
wherein the epitaxial layers have end portions with a film thicknesses smaller than that of center portions of the epitaxial layers, and
the sidewalls cover the upper surfaces of the end portions of the epitaxial layers,
wherein the sidewalls include a second insulating film in contact with the side surfaces of the first gate electrode and a third insulating film that covers the second insulating film, and
the third insulating film covers the upper surfaces of the epitaxial layers, and is in contact with the upper surfaces of the epitaxial layers.

8. The semiconductor device according to claim 7 ,
wherein the upper surfaces of the first source and drain regions are positioned at a region higher than an upper surface of the first gate insulating film, and
the upper surfaces of the second source and drain regions are positioned at a region lower than an upper surface of the

Assignees

• Renesas Electronics Corp

Inventors

• Tsunomura Takaaki
• Yamamoto Yoshiki
• Shinohara Masaaki
• Iwamatsu Toshiaki
• Oda Hidekazu

Classifications

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H01L29/41783

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L29/66477

  Electricity · mapped topic