Systems and techniques for accessing multiple memory cells concurrently

Patent metadata

Field	Value
Publication number	US-11705194-B2
Application number	US-202217733683-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Dec 19, 2018
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

First claim

The invention claimed is:

1. A method, comprising:
identifying a first memory cell of a memory tile to program using a write operation;
identifying a second memory cell of the memory tile to access using a write operation or a read operation;
determining that accessing the second memory cell concurrently with programming the first memory cell is permitted on the memory tile during an access operation duration;
programming the first memory cell of the memory tile during the access operation duration; and
accessing the second memory cell of the memory tile concurrently with programming the first memory cell during the access operation duration based at least in part on determining that accessing the second memory cell concurrently with programming the first memory cell is permitted.

2. The method of claim 1 , wherein accessing the second memory cell concurrently with programming the first memory cell comprises programming the first memory cell using a first programming pulse during the access operation duration and programming the second memory cell using a second programming pulse during the access operation duration concurrently with programming the first memory cell.

3. The method of claim 2 , further comprising:
delaying an application of the first programming pulse or the second programming pulse during the access operation duration based at least in part on a voltage applied to an unselected memory cell exceeding a programming threshold on the memory tile during the access operation duration, wherein accessing the second memory cell concurrently with programming the first memory cell during the access operation duration is based at least in part on delaying the first programming pulse.

4. The method of claim 3 , further comprising:
identifying a first bit transition of the first memory cell during the write operation and a second bit transition of the second memory cell during the write operation; and
determining that a combination of the first bit transition and the second bit transition is would result in the voltage applied to the unselected memory cell exceeding the programming threshold on the memory tile during the access operation duration, wherein delaying the application of the first programming pulse or the second programming pulse is based at least in part on determining that the combination of the first bit transition and the second bit transition would result in the voltage applied to the unselected memory cell exceeding the programming threshold.

5. The method of claim 2 , further comprising:
refraining from applying the first programming pulse or the second programming pulse during the access operation duration based at least in part on a combination of the first programming pulse and the second programming pulse applying a voltage to an unselected memory cell that exceeds a programming threshold of the unselected memory cell.

6. The method of claim 1 , further comprising:
determining that the first memory cell is coupled with different access lines than the second memory cell, wherein accessing the second memory cell concurrently with programming the first memory cell during the access operation duration is based at least in part on determining that the first memory cell is coupled with the different access lines than the second memory cell.

7. The method of claim 1 , wherein accessing the second memory cell concurrently with programming the first memory cell comprises programming the first memory cell using a programming pulse during the access operation duration and reading the second memory cell using a read pulse during the access operation duration concurrently with programming the first memory cell.

8. The method of claim 7 , further comprising:
selecting a polarity of the read pulse applied to the second memory cell during the access operation duration based at least in part on a characteristic of the programming pulse applied to the first memory cell during the access operation duration.

9. The method of claim 8 , wherein the characteristic of the programming pulse is a polarity of the programming pulse, a location to which the programming pulse is being applied, a bit transition associated with the programming pulse, or a combination thereof.

10. The method of claim 7 , further comprising:
inverting data read from the second memory cell based at least in part on the read pulse having a negative polarity; and
outputting the inverted data.

11. The method of claim 7 , further comprising:
delaying an application of the programming pulse or the read pulse during the access operation duration based at least in part on a voltage applied to an unselected memory cell exceeding a programming threshold on the memory tile during the access operation duration, wherein accessing the second memory cell concurrently with programming the first memory cell during the access operation duration is based at least in part on delaying the programming pulse or the read pulse.

12. The method of claim 11 , further comprising:
determining that a combination of the programming pulse and the read pulse would result in the voltage applied to the unselected memory cell exceeding the programming threshold on the memory tile during the access operation duration, wherein delaying the programming pulse or the read pulse is based at least in part on determining that the combination of the programming pulse and the read pulse would result in the voltage applied to the unselected memory cell exceeding the programming threshold.

13. The method of claim 7 , further comprising:
refraining from applying the programming pulse or the read pulse during the access operation duration based at least in part on a combination of the programming pulse and the read pulse applying a voltage to an unselected memory cell that exceeds a programming threshold of the unselected memory cell.

14. The method of claim 1 , further comprising:
identifying that a combination of a programming pulse and a read pulse would result in a voltage applied to an unselected memory cell that does not satisfy a programming threshold during the access operation duration, wherein determining that accessing the second memory cell concurrently with programming the first memory cell is permitted is based at least in part on identifying that the voltage does not satisfy the programming threshold.

15. The method of claim 1 , further comprising:
identifying that accessing a pairing of the first memory cell and the second memory cell concurrently would result in a voltage applied to an unselected memory cell that does not satisfy a programming threshold during the access operation duration, wherein determining that accessing the second memory cell concurrently with programming the first memory cell is permitted is based at least in part on identifying that the voltage does not satisfy the programming threshold.

16. The method of claim 1 , further comprising:
comparing a combination of a programming pulse and a read pulse with a set of preconfigured permissible combinations, wherein determining that accessing the second memory cell concurrently with programming the first memory cell is permitted is based at least in part on comparing the combination with the set of preconfigured permissible combinations.

17. An apparatus, comprising:
a memory tile comprising a first memory cell and a second memory cell; and
a controller coupled with the memory tile, the controller configured to cause the apparatus to:
identify the first memory cell of the memory tile to program using a write operation;
identify the second m

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• G11C13/003 Primary

  Cell access · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title