Memory arrays and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-11700729-B2
Application number	US-202117524913-A
Country	US
Kind code	B2
Filing date	Nov 12, 2021
Priority date	Aug 25, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers;
forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions;
forming sacrificial material in the trenches;
forming bridges above the stack and the sacrificial material, the bridges extending across the trenches laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions; and
replacing the sacrificial material in the trenches with intervening material that is directly under and longitudinally-between the bridges.

2. The method of claim 1 wherein material of the bridges is atop and extends laterally all across individual of the memory-block regions during the replacing.

3. The method of claim 2 wherein the material of the bridges covers all of tops of the memory-block regions during the replacing.

4. The method of claim 1 comprising forming the sacrificial material to have a top surface that is elevationally coincident with a top surface of the stack.

5. The method of claim 1 comprising forming the sacrificial material to have a top surface that is below a top surface of the stack.

6. The method of claim 1 comprising forming the sacrificial material and the stack to individually have a top surface that is planar.

7. The method of claim 6 comprising forming the top surfaces of the sacrificial material and the stack to be co-planar.

8. The method of claim 1 wherein material of the bridges is directly against and of the same composition as insulative material of a top insulative second tier of the stack.

9. The method of claim 1 wherein material of the bridges is of different composition of all material of the vertically-alternating first tiers and second tiers.

10. The method of claim 9 wherein the bridge material comprises carbon-doped silicon nitride.

11. The method of claim 1 comprising removing all of the bridges after the replacing.

12. The method of claim 1 wherein at least some material of the bridges remains extending across the trenches in a finished construction of the memory array.

13. The method of claim 12 comprising reducing vertical thickness of the bridges after the replacing.

14. The method of claim 1 comprising forming the sacrificial material to comprise at least one of spin-on-carbon, boron and/or phosphorous doped silicon dioxide, aluminum oxide, and elemental-form tungsten.

15. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the first tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual first tiers, conducting material of the first tiers being formed after forming the bridges.

16. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the first tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual first tiers, conducting material of the first tiers being formed before forming the bridges.

17. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the first tiers comprising first sacrificial material;
forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions;
forming second sacrificial material in the trenches;
forming bridges above the stack and the second sacrificial material, the bridges extending across the trenches laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions;
isotropically etching away the second sacrificial material selectively relative to the bridges and the second tiers;
isotropically etching away and replacing the first sacrificial material that is in the first tiers with conducting material of individual conductive lines; and
forming intervening material in the trenches directly under and longitudinally-between the bridges between the immediately-laterally-adjacent memory-block regions.

18. The method of claim 17 wherein the first and second sacrificial materials are of different compositions relative one another.

19. The method of claim 17 wherein the first and second sacrificial materials are of the same composition relative one another.

20. The method of claim 17 wherein the isotropically etching away the second sacrificial material selectively relative to the bridges and the second tiers is also conducted selectively relative to the first tiers.

Assignees

• Micron Technology Inc

Inventors

• Hu Yi
• Abdelrahaman Ramey M
• Bilik Narula
• Billingsley Daniel
• Bo Zhenyu
• Kash Joan M
• King Matthew J
• Li Andrew
• Neumeyer David
• Ng Wei Yeeng
• Pak Yung K
• Tiwari Chandra
• Wang Yiping
• Williamson Lance
• Zhang Xiaosong

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title