Multiplexer with highly linear analog switch

Patent metadata

Field	Value
Publication number	US-11699995-B2
Application number	US-202117531654-A
Country	US
Kind code	B2
Filing date	Nov 19, 2021
Priority date	Dec 2, 2020
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

First claim

The invention claimed is:

1. A multiplexer, comprising:
an input terminal;
an output terminal;
a main switch coupled between the input terminal and the output terminal and configured to pass a signal between the input terminal and the output terminal, wherein the main switch is a transistor including:
a source terminal coupled to the input terminal;
a drain terminal coupled to the output terminal; and
a gate terminal;

a first boot strap circuit including a first bootstrap capacitor and configured to couple the first bootstrap capacitor to the main switch during a first phase and to decouple the first bootstrap capacitor from the main switch during a second phase; and
a second boot strap circuit including a second bootstrap capacitor and configured to couple the second bootstrap capacitor to the main switch during the second phase and to decouple the second bootstrap capacitor from the main switch during the first phase, wherein during the first phase the first bootstrap capacitor is coupled between the source and gate terminals of the transistor and the second bootstrap capacitor is decoupled from the source and gate terminals of the transistor.

2. The multiplexer of claim 1 , wherein during the second phase the second bootstrap capacitor is coupled between the source and gate terminals of the transistor and the first bootstrap capacitor is decoupled from the source and gate terminals of the transistor.

3. The multiplexer of claim 2 , wherein during the first phase the second bootstrap capacitor charges to a supply voltage value, wherein during the second phase the first bootstrap capacitor charges to the supply voltage value.

4. The multiplexer of claim 3 , wherein the first bootstrap circuit includes a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate and source terminals of the transistor during the first and second phases.

5. The multiplexer of claim 4 , wherein the second bootstrap circuit includes a plurality of second switches configured to selectively couple and decouple the second bootstrap capacitor between the gate and source terminals of the transistor during the first and second phases.

6. The multiplexer of claim 5 , wherein the first and second phases alternate in accordance with a clock signal.

7. The multiplexer of claim 4 , wherein the first and second bootstrap circuits collectively maintain a gate to source voltage of the transistor at a constant value during the first and second phases.

8. The multiplexer of claim 7 , wherein the constant value is the supply voltage value.

9. A method, comprising:
coupling a main switch between an input terminal and an output terminal of a multiplexer;
passing a signal between the input terminal and the output terminal;
coupling a first boot strap circuit including a first bootstrap capacitor to the main switch during a first phase and decoupling the first bootstrap capacitor from the main switch during a second phase; and
coupling a second boot strap circuit including a second bootstrap capacitor to the main switch during the second phase and decoupling the second bootstrap capacitor from the main switch during the first phase;
coupling a source terminal of the main switch to the input terminal and coupling a drain terminal of the main switch to the output terminal; and
coupling, during the first phase, the first bootstrap capacitor between the source terminal and a gate terminal of the main switch and decoupling the second bootstrap capacitor from the source and gate terminals of the main switch.

10. The method of claim 9 , comprising coupling, during the second phase, the second bootstrap capacitor between the source and gate terminals of the main switch and decoupling the first bootstrap capacitor from the source and gate terminals of the main switch.

11. A device, comprising:
an input terminal;
an output terminal;
a transistor having a source, drain, and gate, the source coupled to the input terminal and the drain coupled to the output terminal, the transistor configured to pass a signal between the input terminal and the output terminal;
a first boot strap circuit including a first bootstrap capacitor and configured to couple the first bootstrap capacitor to the transistor during a first phase and to decouple the first bootstrap capacitor from the transistor during a second phase; and
a second boot strap circuit including a second bootstrap capacitor and configured to couple the second bootstrap capacitor to the transistor during the second phase and to decouple the second bootstrap capacitor from the transistor during the first phase, wherein during the first phase the first bootstrap capacitor is coupled between the source and gate terminals of the transistor and the second bootstrap capacitor is decoupled from the source and gate terminals of the transistor.

12. The device of 11 , wherein during the second phase the second bootstrap capacitor is coupled between the source and gate terminals of the transistor and the first bootstrap capacitor is decoupled from the source and gate terminals of the transistor.

13. The device of claim 12 , wherein during the first phase the second bootstrap capacitor charges to a supply voltage value, wherein during the second phase the first bootstrap capacitor charges to the supply voltage value.

14. The device of claim 13 , wherein the first bootstrap circuit includes a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate and source terminals of the transistor during the first and second phases.

15. The device of claim 11 , wherein the first and second phases alternate in accordance with a clock signal.

16. The device of claim 11 , wherein the first and second bootstrap circuits collectively maintain a gate to source voltage of the transistor at a constant value during the first and second phases.

17. The method of claim 9 , wherein the first and second phases alternate in accordance with a clock signal.

18. The method of claim 9 , wherein the first and second bootstrap circuits collectively maintain a gate to source voltage of the main switch at a constant value during the first and second phases.

19. The method of claim 9 , wherein the first bootstrap circuit includes a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate and source terminals of the main switch during the first and second phases, wherein the second bootstrap circuit includes a plurality of second switches configured to selectively couple and decouple the second bootstrap capacitor between the gate and source terminals of the main switch during the first and second phases.

Assignees

• St Microelectronics Int Nv

Inventors

• Garg Vaibhav
• Jain Abhishek
• Kumar Anand

Classifications

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title

• H03K19/01735

  by bootstrapping, i.e. by positive feed-back · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title