Integrated circuit devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11699759-B2
Application number	US-202117545072-A
Country	US
Kind code	B2
Filing date	Dec 8, 2021
Priority date	May 27, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin shaped active region protruding from a substrate and extending in a first direction;
first, second, and third semiconductor patterns on the fin shaped active region, the first to third semiconductor patterns being spaced apart from each other in a vertical direction;
a gate electrode surrounding the first to third semiconductor patterns and extending in a second direction that is perpendicular to the first direction, the gate electrode comprising:
a main gate portion extending on the third semiconductor pattern in the second direction;
a first sub-gate portion between the fin shaped active region and the first semiconductor pattern;
a second sub-gate portion between the first semiconductor pattern and the second semiconductor pattern; and
a third sub-gate portion between the second semiconductor pattern and the third semiconductor pattern, the third sub-gate portion comprising a sub-gate center portion, and sub-gate edge portions comprising opposing end portions of the third sub-gate portion, respectively, in the second direction;

source/drain regions on opposing sides of the first to third semiconductor patterns, respectively, the source/drain regions being connected to the first to third semiconductor patterns; and
a plurality of inner spacers between side surfaces of the first to third sub-gate portions and the source/drain regions,
wherein, in a horizontal cross-sectional view, a first width of the sub-gate center portion in the first direction is less than a second width of one of the sub-gate edge portions in the first direction, and
wherein a third width of the third sub-gate portion in the first direction is less than a fourth width of the first sub-gate portion in the first direction.

2. The integrated circuit device of claim 1 ,
wherein a sidewall of the first sub-gate portion is sloped, and
wherein a sidewall of the third sub-gate portion extends substantially vertically.

3. The integrated circuit device of claim 1 , wherein the plurality of inner spacers comprises:
a first inner spacer on the side surface of the first sub-gate portion;
a second inner spacer on the side surface of the second sub-gate portion; and
a third inner spacer on the side surface of the third sub-gate portion, the third inner spacer being vertically overlapped by the main gate portion.

4. The integrated circuit device of claim 3 , wherein a sidewall of the first inner spacer that is in contact with the source/drain regions includes a curved sidewall.

5. The integrated circuit device of claim 1 , wherein a width of a top of the third semiconductor pattern in the first direction is greater than a width of a bottom of the third semiconductor pattern in the first direction.

6. The integrated circuit device of claim 1 , further comprising a spacer structure on a sidewall of the main gate portion,
wherein the spacer structure does not vertically overlap the third sub-gate portion.

7. The integrated circuit device of claim 6 , wherein the one of the sub-gate edge portions comprises a tail portion adjacent to one of source/drain regions and protruding toward the one of source/drain regions.

8. The integrated circuit device of claim 7 ,
wherein the tail portion of the one of the sub-gate edge portions comprises a first side surface and a second side surface that are connected to each other at an angle,
wherein the first side surface is in contact with the spacer structure, and
wherein the second side surface is in contact with the one of source/drain regions.

9. The integrated circuit device of claim 8 ,
wherein each of the source/drain regions comprises a protrusion portion protruding outward, and
wherein the protrusion portion faces the second side surface of the tail portion of the one of the sub-gate edge portions.

10. An integrated circuit device comprising:
a fin shaped active region protruding from a substrate and extending in a first direction;
a plurality of semiconductor patterns on the fin shaped active region, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction;
a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction that is perpendicular to the first direction, the gate electrode comprising:
a main gate portion extending on an uppermost semiconductor pattern of the plurality of semiconductor patterns in the second direction; and
a plurality of sub-gate portions between the fin shaped active region and lowermost semiconductor pattern of the plurality of semiconductor patterns and between two adjacent ones among the plurality of semiconductor patterns, each sub-gate portion comprising a sub-gate center portion, and sub-gate edge portions comprising opposing end portions of the sub-gate portion, respectively, in the second direction;

source/drain regions on opposing sides of the plurality of semiconductor patterns, respectively, the source/drain regions being connected to the plurality of semiconductor patterns; and
a plurality of inner spacers between side surfaces of the plurality of sub-gate portions and the source/drain regions,
wherein, in a horizontal cross-sectional view, a first width of the sub-gate center portion in the first direction is less than a second width of one of the sub-gate edge portions in the first direction, and
wherein a third width of an uppermost sub-gate portion of the plurality of sub-gate portions in the first direction is less than a fourth width of the main gate portion in the first direction.

11. The integrated circuit device of claim 10 ,
wherein a sidewall of a lowermost sub-gate portion of the plurality of sub-gate portions is sloped, and
wherein a sidewall of the uppermost sub-gate portion extends substantially vertically.

12. The integrated circuit device of claim 10 , wherein the inner spacer on the side surface of a lowermost sub-gate portion of the plurality of sub-gate portions includes a curved sidewall.

13. The integrated circuit device of claim 10 , wherein a width of a top of the uppermost semiconductor pattern in the first direction is greater than a width of a bottom of the uppermost semiconductor pattern in the first direction.

14. The integrated circuit device of claim 10 , further comprising a spacer structure on a sidewall of the main gate portion,
wherein the sub-gate edge portion comprises a tail portion adjacent to one of the source/drain regions and protruding toward the one of the source/drain regions.

15. The integrated circuit device of claim 14 ,
wherein the tail portion of the sub-gate edge portion comprises a first side surface and a second side surface that are connected to each other at an angle,
wherein the first side surface is in contact with the spacer structure, and
wherein the second side surface is in contact with the one of the source/drain regions.

16. The integrated circuit device of claim 15 ,
wherein each of the source/drain regions comprises a protrusion portion protruding outward, and
wherein the protrusion portion faces the second side surface of the tail portion of the sub-gate edge portion.

17. An integrated circuit device comprising:
a substrate including a first region and a second region;
a first transistor on the first region of the substrate; and
a second transistor on the second region of the substrate,
wherein each of the first and second transistors comprises:
a fin shaped active region protruding from the substrate and extending in a first direction;
a plurality of semi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Seungmin
• Park Junbeom
• Suh Bongseok
• Yang Junggil

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic