Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-11699613-B2
Application number	US-202017137485-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Nov 8, 2017
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

First claim

What is claimed is:

1. A method of forming an integrated circuit device, the method comprising:
sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate, wherein the first epitaxial layer comprises a material different from the second epitaxial layer, and a thickness of the first epitaxial layer is from about 10 Å to about 100 Å;
implanting dopants into the second epitaxial layer to form a preliminary impurity region in the second epitaxial layer;
heating the substrate to convert the preliminary impurity region into an impurity region;
forming a third epitaxial layer on the substrate after heating the substrate;
forming a first trench and a second trench in the third epitaxial layer and the impurity region to define an active in between the first trench and the second trench;
forming a first isolation layer and a second isolation layer in the first trench and the second trench, respectively, wherein the active fin protrudes beyond upper surfaces of the first and second isolation layers such that the first and second isolation layers expose opposing sides of the active fin;
forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin; and
forming a gate electrode traversing the active fin.

2. The method of claim 1 , further comprising measuring a sum of thicknesses of the second and third epitaxial layers by using an upper surface of the first epitaxial layer as a reference line.

3. The method of claim 1 , wherein the first epitaxial layer comprises silicon carbide and/or silicon germanium.

4. The method of claim 1 , wherein a thickness of the second epitaxial layer is from about 1000 Å to about 1500 Å.

5. The method of claim 1 , wherein the impurity region has a crystal defect density lower than a crystal defect density of the preliminary impurity region.

6. The method of claim 1 , wherein an upper portion of the active fin comprises an undoped semiconductor pattern that is a portion of an undoped semiconductor layer.

7. The method of claim 1 , wherein the preliminary impurity region comprises an amorphous structure, and
wherein the impurity region comprises a crystalline structure.

8. A method of forming an integrated circuit device, the method comprising
implanting first dopants into a substrate to form a preliminary impurity region in the substrate, the first dopants having a first conductivity type;
heating the substrate to convert the preliminary impurity region into an impurity region;
forming an undoped semiconductor layer on the substrate after heating the substrate;
forming a first trench and a second trench in the undoped semiconductor layer and the impurity region to define an active fin between the first trench and the second trench;
forming a first isolation layer and a second isolation layer in the first trench and the second trench, respectively, wherein the active fin protrudes beyond upper surfaces of the first and second isolation layers such that the first and second isolation layers expose opposing sides of the active fin;
forming a pair of source/drain regions in the undoped semiconductor layer thereby defining a channel region in the undoped semiconductor layer between the pair of source/drain regions, the pair of source/drain regions including second dopants that have a second conductivity type that is opposite the first conductivity type;
forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin; and
forming a gate electrode traversing the active fin,
wherein the active fin extends longitudinally in a horizontal direction in a plan view,
wherein the channel region comprises a middle portion in the horizontal direction, and the middle portion of the channel region comprises some of the second dopants diffused from the pair of source/drain regions, and
wherein a concentration of the some of the second dopants in the middle portion of the channel region is about 5E18-5E20 atoms/cm 3 after forming the gate electrode.

9. The method of claim 8 , wherein a thickness of the channel region in a vertical direction that is substantially perpendicular to the horizontal direction is about 1.1 times a thickness of one of the pair of source/drain regions in the vertical direction.

10. The method of claim 8 , wherein heating the substrate is performed at an ambient temperature of from about 850° C. to about 950° C. and for from about 20 min to about 50 min.

11. The method of claim 8 , further comprising:
before implanting the first dopants into the substrate, sequentially forming a first epitaxial layer and a second epitaxial layer on a preliminary substrate, wherein the first epitaxial layer comprises a material different from the second epitaxial layer, and wherein the substrate comprises the preliminary substrate, the first epitaxial layer, and the second epitaxial layer; and
measuring a sum of thicknesses of the second epitaxial layer and the undoped semiconductor layer by using an upper surface of the first epitaxial layer as a reference line.

12. The method of claim 8 , wherein the impurity region has a crystal defect density lower than a crystal defect density of the preliminary impurity region.

13. The method of claim 8 , wherein the preliminary impurity region comprises an amorphous structure, and
wherein the impurity region comprises a crystalline structure.

14. A method of forming an integrated circuit device, the method comprising:
sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate;
implanting dopants into the first and second epitaxial layers to form an impurity region;
forming a channel layer on the second epitaxial layer after forming the impurity region;
patterning the channel layer and the second epitaxial layer to form active fins;
forming a gate insulation layer extending on opposing sides and an upper surface of the active fins;
forming a gate electrode traversing the active fins; and
forming a pair of source/drain regions in the active fins on opposite sides of the gate electrode.

15. The method of claim 14 , wherein forming the channel layer comprises forming an undoped semiconductor layer by performing an epitaxial growth process using the second epitaxial layer as a seed layer.

16. The method of claim 14 , wherein forming the active fins comprises forming trenches in the channel layer and the second epitaxial layer, and
wherein the trenches have bottom surfaces spaced apart from the first epitaxial layer.

17. The method of claim 14 , wherein an upper portion of each of the active fins comprises a portion of the second epitaxial layer and a portion of the channel layer.

18. The method of claim 14 , wherein a thickness of the first epitaxial layer is less than a thickness of the second epitaxial layer, and
wherein a thickness of the channel layer is less than the thickness of the second epitaxial layer and greater than the thickness of the first epitaxial layer.

19. The method of claim 14 , wherein forming the impurity region comprises:
implanting first dopants into the substrate to form a preliminary impurity region in the substrate, the first dopants having a first conductivity type; and
heating the substrate to convert the preliminary impurity region into the impurity region, and
wherein the impurity region has a crystal defect density lower than a crystal defect density of the preliminary impurity region.

20. The method of claim 14 , wherein the first epitaxial layer comprises a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Sunguk
• Kim Seokhoon
• Lee Seung Hun
• Xu Yang
• Yoo Jeongho
• Yoo Jongryeol
• Cho Youngdae

Classifications

• H01L21/76232

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L21/02164

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic