Linear equalizer with variable gain

Patent metadata

Field	Value
Publication number	US-9520872-B2
Application number	US-201414581820-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A linear equalizer is configured with load transistors that load a corresponding differential pair of transistors. The linear equalizer is configured to selectively diode connect each load transistor to boost a high frequency gain.

First claim

I claim:

1. An equalizer, comprising;
a current source transistor;
a differential pair of transistors, wherein a source for each differential pair transistor couples to a terminal for the current source transistor;
a pair of load transistors corresponding to the differential pair of transistors, each load transistor having a drain coupled to a drain for the corresponding differential pair transistor;
a pair of capacitors corresponding to the pair of load transistors, each capacitor being coupled between a gate of the corresponding load transistor and a node selected from the group consisting of a power supply node and a ground node; and
a pair of source follower transistors corresponding to the pair of load transistors, each source follower transistor having a gate coupled to the drain of the corresponding load transistor and having a source coupled to the gate of the corresponding load transistor.

2. The equalizer of claim 1 , further comprising a pair of current sources corresponding to the pair of source follower transistors, each current source coupling to a source of the corresponding source follower transistor, each source follower transistor having a drain coupled to the node.

3. The equalizer of claim 1 , wherein the terminals for the differential pair of transistors are configured to form output nodes for a corresponding differential output voltage.

4. The equalizer of claim 1 , wherein each load transistor comprises a PMOS load transistor.

5. The equalizer of claim 1 , further comprising a pair of DC-gain-boosting transistors corresponding to the pair of load transistors, each DC-gain-boosting transistor being configured to respond to a differential input voltage driving the differential pair of transistors by conducting a current in opposition to a current conducted by the corresponding load transistor.

6. The equalizer of claim 5 , wherein the node is the power supply node, and wherein the pair of DC-gain-boosting transistors comprises a pair of PMOS DC-gain-boosting transistors each having a source coupled to the power supply node and having a drain coupled to the drain of the corresponding load transistor.

7. The equalizer of claim 5 , wherein each DC-gain-boosting transistor has a gate coupled to a gate of an opposing one of the load transistors.

8. The equalizer of claim 1 , wherein each load transistor is configured to be diode-connected through the corresponding source follower transistor, and wherein each capacitor is configured to present a low-impedance path to the node that breaks the diode connection for the corresponding load transistor at a zero frequency for the equalizer.

9. The equalizer of claim 1 , wherein the node is the ground node.

10. A method of operating an equalizer, comprising:
in an equalizer including a differential pair of transistors, a current source coupled to a source for each differential pair transistor, and a pair of load transistors corresponding to the differential pair of transistors, each load transistor having a drain coupled to a drain of the corresponding differential pair transistor, steering a tail current from the current source between the differential pair of transistor responsive to a differential input signal to produce a differential output signal across a pair of terminals for the differential pair transistors;
while an instantaneous frequency for the differential input signal is below a first frequency, diode connecting each load transistor to load the differential pair of transistors with a first impedance; and
while the instantaneous frequency for the differential input signal is above the first frequency, breaking the diode connection for each load transistor to load the differential pair of transistors with a second impedance that is greater than the first impedance.

11. The method of claim 10 , wherein breaking the diode connection for each load transistor comprises forming a low impedance path from a gate for each load transistor to a power supply node through a corresponding capacitor.

12. The method of claim 10 , wherein diode connecting each load transistor comprises diode connecting each load transistor through a corresponding source follower transistor.

13. The method of claim 10 , further comprising:
boosting a DC gain for the equalizer by lowering an effective transconductance for each load transistor.

14. The method of claim 13 , wherein lowering the effective transconductance for each load transistor comprises opposing a differential current conducted by the load transistors.

15. An equalizer, comprising:
a differential pair of transistors configured to steer a tail current responsive to a differential input voltage;
a pair of load transistors corresponding to the differential pair of transistors, each load transistor having a drain coupled to a drain for the corresponding differential pair transistor; and
means for selectively diode connecting the drain for each load transistor to its gate while a frequency content for the differential input voltage is below a first frequency for the equalizer, and for selectively breaking the diode connection for each load transistor while the frequency content for the differential input voltage is above the first frequency.

16. The equalizer of claim 15 , wherein the means is configured to diode connect each load transistor through a corresponding source follower transistor.

17. The equalizer of claim 16 , wherein the means is further configured to break the diode connection for each load transistor through a low impedance path from the gate of each load transistor to a node selected from the group consisting of a power supply node and a ground node.

18. The equalizer of claim 15 , wherein the means is further configured to oppose a differential current through each load transistor to boost a DC gain for the equalizer.

Assignees

• Qualcomm Inc

Inventors

• Pandita Bupesh

Classifications

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H03F2203/45712

  the LC comprising a capacitor as shunt · CPC title

• H03F3/45183 Primary

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title